^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * STM32 Timer Encoder and Counter driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) STMicroelectronics 2018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/counter.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mfd/stm32-timers.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TIM_CCMR_CCXS (BIT(8) | BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TIM_CCMR_MASK (TIM_CCMR_CC1S | TIM_CCMR_CC2S | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) TIM_CCMR_IC1F | TIM_CCMR_IC2F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TIM_CCER_MASK (TIM_CCER_CC1P | TIM_CCER_CC1NP | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) TIM_CCER_CC2P | TIM_CCER_CC2NP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct stm32_timer_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) u32 cr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u32 cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u32 smcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u32 arr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct stm32_timer_cnt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct counter_device counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 max_arr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) bool enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct stm32_timer_regs bak;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * enum stm32_count_function - enumerates stm32 timer counter encoder modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * @STM32_COUNT_SLAVE_MODE_DISABLED: counts on internal clock when CEN=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * @STM32_COUNT_ENCODER_MODE_1: counts TI1FP1 edges, depending on TI2FP2 level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * @STM32_COUNT_ENCODER_MODE_2: counts TI2FP2 edges, depending on TI1FP1 level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * @STM32_COUNT_ENCODER_MODE_3: counts on both TI1FP1 and TI2FP2 edges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) enum stm32_count_function {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) STM32_COUNT_SLAVE_MODE_DISABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) STM32_COUNT_ENCODER_MODE_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) STM32_COUNT_ENCODER_MODE_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) STM32_COUNT_ENCODER_MODE_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static enum counter_count_function stm32_count_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) [STM32_COUNT_SLAVE_MODE_DISABLED] = COUNTER_COUNT_FUNCTION_INCREASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) [STM32_COUNT_ENCODER_MODE_1] = COUNTER_COUNT_FUNCTION_QUADRATURE_X2_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) [STM32_COUNT_ENCODER_MODE_2] = COUNTER_COUNT_FUNCTION_QUADRATURE_X2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) [STM32_COUNT_ENCODER_MODE_3] = COUNTER_COUNT_FUNCTION_QUADRATURE_X4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static int stm32_count_read(struct counter_device *counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct counter_count *count, unsigned long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct stm32_timer_cnt *const priv = counter->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) regmap_read(priv->regmap, TIM_CNT, &cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) *val = cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static int stm32_count_write(struct counter_device *counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct counter_count *count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) const unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct stm32_timer_cnt *const priv = counter->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 ceiling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) regmap_read(priv->regmap, TIM_ARR, &ceiling);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (val > ceiling)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return regmap_write(priv->regmap, TIM_CNT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int stm32_count_function_get(struct counter_device *counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct counter_count *count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) size_t *function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct stm32_timer_cnt *const priv = counter->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 smcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) regmap_read(priv->regmap, TIM_SMCR, &smcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) switch (smcr & TIM_SMCR_SMS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) *function = STM32_COUNT_SLAVE_MODE_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) *function = STM32_COUNT_ENCODER_MODE_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) *function = STM32_COUNT_ENCODER_MODE_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) *function = STM32_COUNT_ENCODER_MODE_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int stm32_count_function_set(struct counter_device *counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct counter_count *count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) size_t function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct stm32_timer_cnt *const priv = counter->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 cr1, sms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) switch (function) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) case STM32_COUNT_SLAVE_MODE_DISABLED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) sms = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) case STM32_COUNT_ENCODER_MODE_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) sms = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) case STM32_COUNT_ENCODER_MODE_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) sms = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) case STM32_COUNT_ENCODER_MODE_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) sms = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Store enable status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) regmap_read(priv->regmap, TIM_CR1, &cr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Make sure that registers are updated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Restore the enable status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, cr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static ssize_t stm32_count_direction_read(struct counter_device *counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct counter_count *count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) void *private, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct stm32_timer_cnt *const priv = counter->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) const char *direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u32 cr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) regmap_read(priv->regmap, TIM_CR1, &cr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) direction = (cr1 & TIM_CR1_DIR) ? "backward" : "forward";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return scnprintf(buf, PAGE_SIZE, "%s\n", direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static ssize_t stm32_count_ceiling_read(struct counter_device *counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct counter_count *count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) void *private, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct stm32_timer_cnt *const priv = counter->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u32 arr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) regmap_read(priv->regmap, TIM_ARR, &arr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return snprintf(buf, PAGE_SIZE, "%u\n", arr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static ssize_t stm32_count_ceiling_write(struct counter_device *counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct counter_count *count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) void *private,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) const char *buf, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct stm32_timer_cnt *const priv = counter->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned int ceiling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ret = kstrtouint(buf, 0, &ceiling);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (ceiling > priv->max_arr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* TIMx_ARR register shouldn't be buffered (ARPE=0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) regmap_write(priv->regmap, TIM_ARR, ceiling);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static ssize_t stm32_count_enable_read(struct counter_device *counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct counter_count *count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) void *private, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct stm32_timer_cnt *const priv = counter->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u32 cr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) regmap_read(priv->regmap, TIM_CR1, &cr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return scnprintf(buf, PAGE_SIZE, "%d\n", (bool)(cr1 & TIM_CR1_CEN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static ssize_t stm32_count_enable_write(struct counter_device *counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct counter_count *count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) void *private,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) const char *buf, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct stm32_timer_cnt *const priv = counter->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u32 cr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) bool enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) err = kstrtobool(buf, &enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) regmap_read(priv->regmap, TIM_CR1, &cr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (!(cr1 & TIM_CR1_CEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) clk_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) TIM_CR1_CEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) regmap_read(priv->regmap, TIM_CR1, &cr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (cr1 & TIM_CR1_CEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) clk_disable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* Keep enabled state to properly handle low power states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) priv->enabled = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const struct counter_count_ext stm32_count_ext[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .name = "direction",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .read = stm32_count_direction_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .name = "enable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .read = stm32_count_enable_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .write = stm32_count_enable_write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .name = "ceiling",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .read = stm32_count_ceiling_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .write = stm32_count_ceiling_write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) enum stm32_synapse_action {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) STM32_SYNAPSE_ACTION_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) STM32_SYNAPSE_ACTION_BOTH_EDGES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static enum counter_synapse_action stm32_synapse_actions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) [STM32_SYNAPSE_ACTION_NONE] = COUNTER_SYNAPSE_ACTION_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) [STM32_SYNAPSE_ACTION_BOTH_EDGES] = COUNTER_SYNAPSE_ACTION_BOTH_EDGES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int stm32_action_get(struct counter_device *counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct counter_count *count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct counter_synapse *synapse,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) size_t *action)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) size_t function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) err = stm32_count_function_get(counter, count, &function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) switch (function) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) case STM32_COUNT_SLAVE_MODE_DISABLED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* counts on internal clock when CEN=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) *action = STM32_SYNAPSE_ACTION_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) case STM32_COUNT_ENCODER_MODE_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* counts up/down on TI1FP1 edge depending on TI2FP2 level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (synapse->signal->id == count->synapses[0].signal->id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) *action = STM32_SYNAPSE_ACTION_BOTH_EDGES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) *action = STM32_SYNAPSE_ACTION_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) case STM32_COUNT_ENCODER_MODE_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* counts up/down on TI2FP2 edge depending on TI1FP1 level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (synapse->signal->id == count->synapses[1].signal->id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) *action = STM32_SYNAPSE_ACTION_BOTH_EDGES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) *action = STM32_SYNAPSE_ACTION_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) case STM32_COUNT_ENCODER_MODE_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* counts up/down on both TI1FP1 and TI2FP2 edges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) *action = STM32_SYNAPSE_ACTION_BOTH_EDGES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static const struct counter_ops stm32_timer_cnt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .count_read = stm32_count_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .count_write = stm32_count_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .function_get = stm32_count_function_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .function_set = stm32_count_function_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .action_get = stm32_action_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static struct counter_signal stm32_signals[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .name = "Channel 1 Quadrature A"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .name = "Channel 1 Quadrature B"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static struct counter_synapse stm32_count_synapses[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .actions_list = stm32_synapse_actions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .num_actions = ARRAY_SIZE(stm32_synapse_actions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .signal = &stm32_signals[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .actions_list = stm32_synapse_actions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .num_actions = ARRAY_SIZE(stm32_synapse_actions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .signal = &stm32_signals[1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static struct counter_count stm32_counts = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .name = "Channel 1 Count",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .functions_list = stm32_count_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .num_functions = ARRAY_SIZE(stm32_count_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .synapses = stm32_count_synapses,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .num_synapses = ARRAY_SIZE(stm32_count_synapses),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .ext = stm32_count_ext,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .num_ext = ARRAY_SIZE(stm32_count_ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static int stm32_timer_cnt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct stm32_timer_cnt *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (IS_ERR_OR_NULL(ddata))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) priv->regmap = ddata->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) priv->clk = ddata->clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) priv->max_arr = ddata->max_arr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) priv->counter.name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) priv->counter.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) priv->counter.ops = &stm32_timer_cnt_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) priv->counter.counts = &stm32_counts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) priv->counter.num_counts = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) priv->counter.signals = stm32_signals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) priv->counter.num_signals = ARRAY_SIZE(stm32_signals);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) priv->counter.priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* Register Counter device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return devm_counter_register(dev, &priv->counter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static int __maybe_unused stm32_timer_cnt_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct stm32_timer_cnt *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* Only take care of enabled counter: don't disturb other MFD child */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (priv->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* Backup registers that may get lost in low power mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) regmap_read(priv->regmap, TIM_SMCR, &priv->bak.smcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) regmap_read(priv->regmap, TIM_ARR, &priv->bak.arr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) regmap_read(priv->regmap, TIM_CNT, &priv->bak.cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) regmap_read(priv->regmap, TIM_CR1, &priv->bak.cr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* Disable the counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) clk_disable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return pinctrl_pm_select_sleep_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static int __maybe_unused stm32_timer_cnt_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct stm32_timer_cnt *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ret = pinctrl_pm_select_default_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (priv->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) clk_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* Restore registers that may have been lost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) regmap_write(priv->regmap, TIM_SMCR, priv->bak.smcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) regmap_write(priv->regmap, TIM_ARR, priv->bak.arr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) regmap_write(priv->regmap, TIM_CNT, priv->bak.cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* Also re-enables the counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) regmap_write(priv->regmap, TIM_CR1, priv->bak.cr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static SIMPLE_DEV_PM_OPS(stm32_timer_cnt_pm_ops, stm32_timer_cnt_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) stm32_timer_cnt_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static const struct of_device_id stm32_timer_cnt_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) { .compatible = "st,stm32-timer-counter", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) MODULE_DEVICE_TABLE(of, stm32_timer_cnt_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static struct platform_driver stm32_timer_cnt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .probe = stm32_timer_cnt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .name = "stm32-timer-counter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .of_match_table = stm32_timer_cnt_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .pm = &stm32_timer_cnt_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) module_platform_driver(stm32_timer_cnt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) MODULE_ALIAS("platform:stm32-timer-counter");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) MODULE_DESCRIPTION("STMicroelectronics STM32 TIMER counter driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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