^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * STM32 Low-Power Timer Encoder and Counter driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) STMicroelectronics 2017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Fabrice Gasnier <fabrice.gasnier@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Inspired by 104-quad-8 and stm32-timer-trigger drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/counter.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mfd/stm32-lptimer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct stm32_lptim_cnt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct counter_device counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u32 ceiling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u32 polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u32 quadrature_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) bool enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static int stm32_lptim_is_enabled(struct stm32_lptim_cnt *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) ret = regmap_read(priv->regmap, STM32_LPTIM_CR, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) return FIELD_GET(STM32_LPTIM_ENABLE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static int stm32_lptim_set_enable_state(struct stm32_lptim_cnt *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) val = FIELD_PREP(STM32_LPTIM_ENABLE, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ret = regmap_write(priv->regmap, STM32_LPTIM_CR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (!enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) clk_disable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) priv->enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* LP timer must be enabled before writing CMP & ARR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ret = regmap_write(priv->regmap, STM32_LPTIM_ARR, priv->ceiling);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ret = regmap_write(priv->regmap, STM32_LPTIM_CMP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* ensure CMP & ARR registers are properly written */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) (val & STM32_LPTIM_CMPOK_ARROK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 100, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ret = regmap_write(priv->regmap, STM32_LPTIM_ICR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) STM32_LPTIM_CMPOKCF_ARROKCF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ret = clk_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) priv->enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Start LP timer in continuous mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return regmap_update_bits(priv->regmap, STM32_LPTIM_CR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) STM32_LPTIM_CNTSTRT, STM32_LPTIM_CNTSTRT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static int stm32_lptim_setup(struct stm32_lptim_cnt *priv, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 mask = STM32_LPTIM_ENC | STM32_LPTIM_COUNTMODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) STM32_LPTIM_CKPOL | STM32_LPTIM_PRESC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Setup LP timer encoder/counter and polarity, without prescaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (priv->quadrature_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) val = enable ? STM32_LPTIM_ENC : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) val = enable ? STM32_LPTIM_COUNTMODE : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) val |= FIELD_PREP(STM32_LPTIM_CKPOL, enable ? priv->polarity : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return regmap_update_bits(priv->regmap, STM32_LPTIM_CFGR, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * enum stm32_lptim_cnt_function - enumerates LPTimer counter & encoder modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * @STM32_LPTIM_COUNTER_INCREASE: up count on IN1 rising, falling or both edges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * @STM32_LPTIM_ENCODER_BOTH_EDGE: count on both edges (IN1 & IN2 quadrature)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * In non-quadrature mode, device counts up on active edge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * In quadrature mode, encoder counting scenarios are as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * +---------+----------+--------------------+--------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * | Active | Level on | IN1 signal | IN2 signal |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * | edge | opposite +----------+---------+----------+---------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * | | signal | Rising | Falling | Rising | Falling |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * +---------+----------+----------+---------+----------+---------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * | Rising | High -> | Down | - | Up | - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * | edge | Low -> | Up | - | Down | - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * +---------+----------+----------+---------+----------+---------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * | Falling | High -> | - | Up | - | Down |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * | edge | Low -> | - | Down | - | Up |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * +---------+----------+----------+---------+----------+---------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * | Both | High -> | Down | Up | Up | Down |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * | edges | Low -> | Up | Down | Down | Up |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * +---------+----------+----------+---------+----------+---------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) enum stm32_lptim_cnt_function {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) STM32_LPTIM_COUNTER_INCREASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) STM32_LPTIM_ENCODER_BOTH_EDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static enum counter_count_function stm32_lptim_cnt_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) [STM32_LPTIM_COUNTER_INCREASE] = COUNTER_COUNT_FUNCTION_INCREASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) [STM32_LPTIM_ENCODER_BOTH_EDGE] = COUNTER_COUNT_FUNCTION_QUADRATURE_X4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) enum stm32_lptim_synapse_action {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) STM32_LPTIM_SYNAPSE_ACTION_RISING_EDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) STM32_LPTIM_SYNAPSE_ACTION_FALLING_EDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) STM32_LPTIM_SYNAPSE_ACTION_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static enum counter_synapse_action stm32_lptim_cnt_synapse_actions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* Index must match with stm32_lptim_cnt_polarity[] (priv->polarity) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) [STM32_LPTIM_SYNAPSE_ACTION_RISING_EDGE] = COUNTER_SYNAPSE_ACTION_RISING_EDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) [STM32_LPTIM_SYNAPSE_ACTION_FALLING_EDGE] = COUNTER_SYNAPSE_ACTION_FALLING_EDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) [STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES] = COUNTER_SYNAPSE_ACTION_BOTH_EDGES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) [STM32_LPTIM_SYNAPSE_ACTION_NONE] = COUNTER_SYNAPSE_ACTION_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int stm32_lptim_cnt_read(struct counter_device *counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct counter_count *count, unsigned long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct stm32_lptim_cnt *const priv = counter->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ret = regmap_read(priv->regmap, STM32_LPTIM_CNT, &cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) *val = cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static int stm32_lptim_cnt_function_get(struct counter_device *counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct counter_count *count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) size_t *function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct stm32_lptim_cnt *const priv = counter->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (!priv->quadrature_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) *function = STM32_LPTIM_COUNTER_INCREASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (priv->polarity == STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) *function = STM32_LPTIM_ENCODER_BOTH_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int stm32_lptim_cnt_function_set(struct counter_device *counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct counter_count *count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) size_t function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct stm32_lptim_cnt *const priv = counter->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (stm32_lptim_is_enabled(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) switch (function) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) case STM32_LPTIM_COUNTER_INCREASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) priv->quadrature_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) case STM32_LPTIM_ENCODER_BOTH_EDGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) priv->quadrature_mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) priv->polarity = STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static ssize_t stm32_lptim_cnt_enable_read(struct counter_device *counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct counter_count *count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) void *private, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct stm32_lptim_cnt *const priv = counter->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ret = stm32_lptim_is_enabled(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return scnprintf(buf, PAGE_SIZE, "%u\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static ssize_t stm32_lptim_cnt_enable_write(struct counter_device *counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct counter_count *count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) void *private,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) const char *buf, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct stm32_lptim_cnt *const priv = counter->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) bool enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ret = kstrtobool(buf, &enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* Check nobody uses the timer, or already disabled/enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ret = stm32_lptim_is_enabled(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if ((ret < 0) || (!ret && !enable))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (enable && ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ret = stm32_lptim_setup(priv, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ret = stm32_lptim_set_enable_state(priv, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static ssize_t stm32_lptim_cnt_ceiling_read(struct counter_device *counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct counter_count *count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) void *private, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct stm32_lptim_cnt *const priv = counter->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return snprintf(buf, PAGE_SIZE, "%u\n", priv->ceiling);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static ssize_t stm32_lptim_cnt_ceiling_write(struct counter_device *counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct counter_count *count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) void *private,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) const char *buf, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct stm32_lptim_cnt *const priv = counter->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) unsigned int ceiling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (stm32_lptim_is_enabled(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ret = kstrtouint(buf, 0, &ceiling);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (ceiling > STM32_LPTIM_MAX_ARR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) priv->ceiling = ceiling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static const struct counter_count_ext stm32_lptim_cnt_ext[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .name = "enable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .read = stm32_lptim_cnt_enable_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .write = stm32_lptim_cnt_enable_write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .name = "ceiling",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .read = stm32_lptim_cnt_ceiling_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .write = stm32_lptim_cnt_ceiling_write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static int stm32_lptim_cnt_action_get(struct counter_device *counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct counter_count *count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct counter_synapse *synapse,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) size_t *action)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct stm32_lptim_cnt *const priv = counter->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) size_t function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) err = stm32_lptim_cnt_function_get(counter, count, &function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) switch (function) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) case STM32_LPTIM_COUNTER_INCREASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* LP Timer acts as up-counter on input 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (synapse->signal->id == count->synapses[0].signal->id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) *action = priv->polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) *action = STM32_LPTIM_SYNAPSE_ACTION_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) case STM32_LPTIM_ENCODER_BOTH_EDGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) *action = priv->polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static int stm32_lptim_cnt_action_set(struct counter_device *counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct counter_count *count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct counter_synapse *synapse,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) size_t action)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct stm32_lptim_cnt *const priv = counter->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) size_t function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (stm32_lptim_is_enabled(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) err = stm32_lptim_cnt_function_get(counter, count, &function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* only set polarity when in counter mode (on input 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (function == STM32_LPTIM_COUNTER_INCREASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) && synapse->signal->id == count->synapses[0].signal->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) switch (action) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) case STM32_LPTIM_SYNAPSE_ACTION_RISING_EDGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) case STM32_LPTIM_SYNAPSE_ACTION_FALLING_EDGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) case STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) priv->polarity = action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static const struct counter_ops stm32_lptim_cnt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .count_read = stm32_lptim_cnt_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .function_get = stm32_lptim_cnt_function_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .function_set = stm32_lptim_cnt_function_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .action_get = stm32_lptim_cnt_action_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .action_set = stm32_lptim_cnt_action_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static struct counter_signal stm32_lptim_cnt_signals[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .name = "Channel 1 Quadrature A"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .name = "Channel 1 Quadrature B"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static struct counter_synapse stm32_lptim_cnt_synapses[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .actions_list = stm32_lptim_cnt_synapse_actions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .num_actions = ARRAY_SIZE(stm32_lptim_cnt_synapse_actions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .signal = &stm32_lptim_cnt_signals[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .actions_list = stm32_lptim_cnt_synapse_actions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .num_actions = ARRAY_SIZE(stm32_lptim_cnt_synapse_actions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .signal = &stm32_lptim_cnt_signals[1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* LP timer with encoder */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static struct counter_count stm32_lptim_enc_counts = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .name = "LPTimer Count",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .functions_list = stm32_lptim_cnt_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .num_functions = ARRAY_SIZE(stm32_lptim_cnt_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .synapses = stm32_lptim_cnt_synapses,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .num_synapses = ARRAY_SIZE(stm32_lptim_cnt_synapses),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .ext = stm32_lptim_cnt_ext,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .num_ext = ARRAY_SIZE(stm32_lptim_cnt_ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* LP timer without encoder (counter only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static struct counter_count stm32_lptim_in1_counts = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .name = "LPTimer Count",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .functions_list = stm32_lptim_cnt_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .num_functions = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .synapses = stm32_lptim_cnt_synapses,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .num_synapses = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .ext = stm32_lptim_cnt_ext,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .num_ext = ARRAY_SIZE(stm32_lptim_cnt_ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static int stm32_lptim_cnt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct stm32_lptimer *ddata = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct stm32_lptim_cnt *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (IS_ERR_OR_NULL(ddata))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) priv->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) priv->regmap = ddata->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) priv->clk = ddata->clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) priv->ceiling = STM32_LPTIM_MAX_ARR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* Initialize Counter device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) priv->counter.name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) priv->counter.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) priv->counter.ops = &stm32_lptim_cnt_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (ddata->has_encoder) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) priv->counter.counts = &stm32_lptim_enc_counts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) priv->counter.num_signals = ARRAY_SIZE(stm32_lptim_cnt_signals);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) priv->counter.counts = &stm32_lptim_in1_counts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) priv->counter.num_signals = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) priv->counter.num_counts = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) priv->counter.signals = stm32_lptim_cnt_signals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) priv->counter.priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return devm_counter_register(&pdev->dev, &priv->counter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static int stm32_lptim_cnt_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct stm32_lptim_cnt *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* Only take care of enabled counter: don't disturb other MFD child */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (priv->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ret = stm32_lptim_setup(priv, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ret = stm32_lptim_set_enable_state(priv, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* Force enable state for later resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) priv->enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return pinctrl_pm_select_sleep_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static int stm32_lptim_cnt_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct stm32_lptim_cnt *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ret = pinctrl_pm_select_default_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (priv->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) priv->enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ret = stm32_lptim_setup(priv, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) ret = stm32_lptim_set_enable_state(priv, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static SIMPLE_DEV_PM_OPS(stm32_lptim_cnt_pm_ops, stm32_lptim_cnt_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) stm32_lptim_cnt_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static const struct of_device_id stm32_lptim_cnt_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) { .compatible = "st,stm32-lptimer-counter", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) MODULE_DEVICE_TABLE(of, stm32_lptim_cnt_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static struct platform_driver stm32_lptim_cnt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .probe = stm32_lptim_cnt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .name = "stm32-lptimer-counter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .of_match_table = stm32_lptim_cnt_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .pm = &stm32_lptim_cnt_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) module_platform_driver(stm32_lptim_cnt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) MODULE_ALIAS("platform:stm32-lptimer-counter");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) MODULE_DESCRIPTION("STMicroelectronics STM32 LPTIM counter driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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