Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2020 Microchip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Author: Kamel Bouhara <kamel.bouhara@bootlin.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/counter.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <soc/at91/atmel_tcb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define ATMEL_TC_CMR_MASK	(ATMEL_TC_LDRA_RISING | ATMEL_TC_LDRB_FALLING | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 				 ATMEL_TC_ETRGEDG_RISING | ATMEL_TC_LDBDIS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 				 ATMEL_TC_LDBSTOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define ATMEL_TC_QDEN			BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define ATMEL_TC_POSEN			BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) struct mchp_tc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	const struct atmel_tcb_config *tc_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	struct counter_device counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	int qdec_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	int num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	int channel[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	bool trig_inverted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) enum mchp_tc_count_function {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	MCHP_TC_FUNCTION_INCREASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	MCHP_TC_FUNCTION_QUADRATURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) static enum counter_count_function mchp_tc_count_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	[MCHP_TC_FUNCTION_INCREASE] = COUNTER_COUNT_FUNCTION_INCREASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	[MCHP_TC_FUNCTION_QUADRATURE] = COUNTER_COUNT_FUNCTION_QUADRATURE_X4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) enum mchp_tc_synapse_action {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	MCHP_TC_SYNAPSE_ACTION_NONE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	MCHP_TC_SYNAPSE_ACTION_RISING_EDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	MCHP_TC_SYNAPSE_ACTION_FALLING_EDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	MCHP_TC_SYNAPSE_ACTION_BOTH_EDGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static enum counter_synapse_action mchp_tc_synapse_actions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	[MCHP_TC_SYNAPSE_ACTION_NONE] = COUNTER_SYNAPSE_ACTION_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	[MCHP_TC_SYNAPSE_ACTION_RISING_EDGE] = COUNTER_SYNAPSE_ACTION_RISING_EDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	[MCHP_TC_SYNAPSE_ACTION_FALLING_EDGE] = COUNTER_SYNAPSE_ACTION_FALLING_EDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	[MCHP_TC_SYNAPSE_ACTION_BOTH_EDGE] = COUNTER_SYNAPSE_ACTION_BOTH_EDGES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static struct counter_signal mchp_tc_count_signals[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		.id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		.name = "Channel A",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		.id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		.name = "Channel B",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) static struct counter_synapse mchp_tc_count_synapses[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		.actions_list = mchp_tc_synapse_actions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		.num_actions = ARRAY_SIZE(mchp_tc_synapse_actions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		.signal = &mchp_tc_count_signals[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		.actions_list = mchp_tc_synapse_actions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		.num_actions = ARRAY_SIZE(mchp_tc_synapse_actions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		.signal = &mchp_tc_count_signals[1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static int mchp_tc_count_function_get(struct counter_device *counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 				      struct counter_count *count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 				      size_t *function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	struct mchp_tc_data *const priv = counter->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	if (priv->qdec_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		*function = MCHP_TC_FUNCTION_QUADRATURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		*function = MCHP_TC_FUNCTION_INCREASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static int mchp_tc_count_function_set(struct counter_device *counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 				      struct counter_count *count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 				      size_t function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	struct mchp_tc_data *const priv = counter->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	u32 bmr, cmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	regmap_read(priv->regmap, ATMEL_TC_BMR, &bmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), &cmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	/* Set capture mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	cmr &= ~ATMEL_TC_WAVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	switch (function) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	case MCHP_TC_FUNCTION_INCREASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		priv->qdec_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		/* Set highest rate based on whether soc has gclk or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		bmr &= ~(ATMEL_TC_QDEN | ATMEL_TC_POSEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		if (priv->tc_cfg->has_gclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			cmr |= ATMEL_TC_TIMER_CLOCK2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			cmr |= ATMEL_TC_TIMER_CLOCK1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		/* Setup the period capture mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		cmr |=  ATMEL_TC_CMR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		cmr &= ~(ATMEL_TC_ABETRG | ATMEL_TC_XC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	case MCHP_TC_FUNCTION_QUADRATURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		if (!priv->tc_cfg->has_qdec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		/* In QDEC mode settings both channels 0 and 1 are required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		if (priv->num_channels < 2 || priv->channel[0] != 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		    priv->channel[1] != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			pr_err("Invalid channels number or id for quadrature mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		priv->qdec_mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		bmr |= ATMEL_TC_QDEN | ATMEL_TC_POSEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		cmr |= ATMEL_TC_ETRGEDG_RISING | ATMEL_TC_ABETRG | ATMEL_TC_XC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	regmap_write(priv->regmap, ATMEL_TC_BMR, bmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), cmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	/* Enable clock and trigger counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], CCR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		     ATMEL_TC_CLKEN | ATMEL_TC_SWTRG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	if (priv->qdec_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		regmap_write(priv->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			     ATMEL_TC_REG(priv->channel[1], CMR), cmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		regmap_write(priv->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			     ATMEL_TC_REG(priv->channel[1], CCR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 			     ATMEL_TC_CLKEN | ATMEL_TC_SWTRG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int mchp_tc_count_signal_read(struct counter_device *counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 				     struct counter_signal *signal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 				     enum counter_signal_value *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	struct mchp_tc_data *const priv = counter->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	bool sigstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	u32 sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], SR), &sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	if (priv->trig_inverted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		sigstatus = (sr & ATMEL_TC_MTIOB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		sigstatus = (sr & ATMEL_TC_MTIOA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	*val = sigstatus ? COUNTER_SIGNAL_HIGH : COUNTER_SIGNAL_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int mchp_tc_count_action_get(struct counter_device *counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 				    struct counter_count *count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 				    struct counter_synapse *synapse,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 				    size_t *action)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	struct mchp_tc_data *const priv = counter->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	u32 cmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), &cmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	switch (cmr & ATMEL_TC_ETRGEDG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		*action = MCHP_TC_SYNAPSE_ACTION_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	case ATMEL_TC_ETRGEDG_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		*action = MCHP_TC_SYNAPSE_ACTION_RISING_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	case ATMEL_TC_ETRGEDG_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		*action = MCHP_TC_SYNAPSE_ACTION_FALLING_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	case ATMEL_TC_ETRGEDG_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		*action = MCHP_TC_SYNAPSE_ACTION_BOTH_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int mchp_tc_count_action_set(struct counter_device *counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 				    struct counter_count *count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 				    struct counter_synapse *synapse,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 				    size_t action)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	struct mchp_tc_data *const priv = counter->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	u32 edge = ATMEL_TC_ETRGEDG_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	/* QDEC mode is rising edge only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	if (priv->qdec_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	switch (action) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	case MCHP_TC_SYNAPSE_ACTION_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		edge = ATMEL_TC_ETRGEDG_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	case MCHP_TC_SYNAPSE_ACTION_RISING_EDGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		edge = ATMEL_TC_ETRGEDG_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	case MCHP_TC_SYNAPSE_ACTION_FALLING_EDGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		edge = ATMEL_TC_ETRGEDG_FALLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	case MCHP_TC_SYNAPSE_ACTION_BOTH_EDGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		edge = ATMEL_TC_ETRGEDG_BOTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	return regmap_write_bits(priv->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 				ATMEL_TC_REG(priv->channel[0], CMR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 				ATMEL_TC_ETRGEDG, edge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static int mchp_tc_count_read(struct counter_device *counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			      struct counter_count *count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			      unsigned long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	struct mchp_tc_data *const priv = counter->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	u32 cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], CV), &cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	*val = cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static struct counter_count mchp_tc_counts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		.id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		.name = "Timer Counter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		.functions_list = mchp_tc_count_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		.num_functions = ARRAY_SIZE(mchp_tc_count_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		.synapses = mchp_tc_count_synapses,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		.num_synapses = ARRAY_SIZE(mchp_tc_count_synapses),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static const struct counter_ops mchp_tc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	.signal_read  = mchp_tc_count_signal_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	.count_read   = mchp_tc_count_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	.function_get = mchp_tc_count_function_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	.function_set = mchp_tc_count_function_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	.action_get   = mchp_tc_count_action_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	.action_set   = mchp_tc_count_action_set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static const struct atmel_tcb_config tcb_rm9200_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		.counter_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static const struct atmel_tcb_config tcb_sam9x5_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		.counter_width = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static const struct atmel_tcb_config tcb_sama5d2_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		.counter_width = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		.has_gclk = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		.has_qdec = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static const struct atmel_tcb_config tcb_sama5d3_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		.counter_width = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		.has_qdec = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static const struct of_device_id atmel_tc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	{ .compatible = "atmel,at91rm9200-tcb", .data = &tcb_rm9200_config, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	{ .compatible = "atmel,at91sam9x5-tcb", .data = &tcb_sam9x5_config, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	{ .compatible = "atmel,sama5d2-tcb", .data = &tcb_sama5d2_config, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	{ .compatible = "atmel,sama5d3-tcb", .data = &tcb_sama5d3_config, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static void mchp_tc_clk_remove(void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	clk_disable_unprepare((struct clk *)ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static int mchp_tc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	const struct atmel_tcb_config *tcb_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	struct mchp_tc_data *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	char clk_name[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	struct clk *clk[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	int channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	match = of_match_node(atmel_tc_of_match, np->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	tcb_config = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	if (!tcb_config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		dev_err(&pdev->dev, "No matching parent node found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	regmap = syscon_node_to_regmap(np->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	/* max. channels number is 2 when in QDEC mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	priv->num_channels = of_property_count_u32_elems(np, "reg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	if (priv->num_channels < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		dev_err(&pdev->dev, "Invalid or missing channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	/* Register channels and initialize clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	for (i = 0; i < priv->num_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		ret = of_property_read_u32_index(np, "reg", i, &channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		if (ret < 0 || channel > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 			return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		priv->channel[i] = channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		snprintf(clk_name, sizeof(clk_name), "t%d_clk", channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		clk[i] = of_clk_get_by_name(np->parent, clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		if (IS_ERR(clk[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 			/* Fallback to t0_clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 			clk[i] = of_clk_get_by_name(np->parent, "t0_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 			if (IS_ERR(clk[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 				return PTR_ERR(clk[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		ret = clk_prepare_enable(clk[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		ret = devm_add_action_or_reset(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 					       mchp_tc_clk_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 					       clk[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		dev_dbg(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 			"Initialized capture mode on channel %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 			channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	priv->tc_cfg = tcb_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	priv->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	priv->counter.name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	priv->counter.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	priv->counter.ops = &mchp_tc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	priv->counter.num_counts = ARRAY_SIZE(mchp_tc_counts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	priv->counter.counts = mchp_tc_counts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	priv->counter.num_signals = ARRAY_SIZE(mchp_tc_count_signals);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	priv->counter.signals = mchp_tc_count_signals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	priv->counter.priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	return devm_counter_register(&pdev->dev, &priv->counter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static const struct of_device_id mchp_tc_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	{ .compatible = "microchip,tcb-capture", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	{ /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) MODULE_DEVICE_TABLE(of, mchp_tc_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static struct platform_driver mchp_tc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	.probe = mchp_tc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		.name = "microchip-tcb-capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 		.of_match_table = mchp_tc_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) module_platform_driver(mchp_tc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) MODULE_AUTHOR("Kamel Bouhara <kamel.bouhara@bootlin.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) MODULE_DESCRIPTION("Microchip TCB Capture driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) MODULE_LICENSE("GPL v2");