^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * arch/arm/mach-vt8500/timer.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This file is copied and modified from the original timer.c provided by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Alexey Charkov. Minor changes have been made for Device Tree Support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define VT8500_TIMER_OFFSET 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define VT8500_TIMER_HZ 3000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TIMER_MATCH_VAL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TIMER_COUNT_VAL 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TIMER_STATUS_VAL 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TIMER_IER_VAL 0x001c /* interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TIMER_CTRL_VAL 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TIMER_AS_VAL 0x0024 /* access status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TIMER_COUNT_R_ACTIVE (1 << 5) /* not ready for read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TIMER_COUNT_W_ACTIVE (1 << 4) /* not ready for write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TIMER_MATCH_W_ACTIVE (1 << 0) /* not ready for write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MIN_OSCR_DELTA 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static void __iomem *regbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static u64 vt8500_timer_read(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int loops = msecs_to_loops(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) writel(3, regbase + TIMER_CTRL_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) while ((readl((regbase + TIMER_AS_VAL)) & TIMER_COUNT_R_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) && --loops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return readl(regbase + TIMER_COUNT_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static struct clocksource clocksource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .name = "vt8500_timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .rating = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .read = vt8500_timer_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .mask = CLOCKSOURCE_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .flags = CLOCK_SOURCE_IS_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int vt8500_timer_set_next_event(unsigned long cycles,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int loops = msecs_to_loops(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u64 alarm = clocksource.read(&clocksource) + cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) while ((readl(regbase + TIMER_AS_VAL) & TIMER_MATCH_W_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) && --loops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) writel((unsigned long)alarm, regbase + TIMER_MATCH_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if ((signed)(alarm - clocksource.read(&clocksource)) <= MIN_OSCR_DELTA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) writel(1, regbase + TIMER_IER_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static int vt8500_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) writel(readl(regbase + TIMER_CTRL_VAL) | 1, regbase + TIMER_CTRL_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) writel(0, regbase + TIMER_IER_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static struct clock_event_device clockevent = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .name = "vt8500_timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .features = CLOCK_EVT_FEAT_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .rating = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .set_next_event = vt8500_timer_set_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .set_state_shutdown = vt8500_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .set_state_oneshot = vt8500_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static irqreturn_t vt8500_timer_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct clock_event_device *evt = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) writel(0xf, regbase + TIMER_STATUS_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) evt->event_handler(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int __init vt8500_timer_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int timer_irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) regbase = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (!regbase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) pr_err("%s: Missing iobase description in Device Tree\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) timer_irq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (!timer_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) pr_err("%s: Missing irq description in Device Tree\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) writel(1, regbase + TIMER_CTRL_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) writel(0xf, regbase + TIMER_STATUS_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) writel(~0, regbase + TIMER_MATCH_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ret = clocksource_register_hz(&clocksource, VT8500_TIMER_HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) pr_err("%s: clocksource_register failed for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) __func__, clocksource.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) clockevent.cpumask = cpumask_of(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ret = request_irq(timer_irq, vt8500_timer_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) IRQF_TIMER | IRQF_IRQPOLL, "vt8500_timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) &clockevent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) pr_err("%s: setup_irq failed for %s\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) clockevent.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) clockevents_config_and_register(&clockevent, VT8500_TIMER_HZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MIN_OSCR_DELTA * 2, 0xf0000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) TIMER_OF_DECLARE(vt8500, "via,vt8500-timer", vt8500_timer_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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