Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2007-2009 ST-Ericsson AB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Timer COH 901 328, runs the OS timer interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Author: Linus Walleij <linus.walleij@stericsson.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/timex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /* Generic stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <asm/mach/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * APP side special timer registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * This timer contains four timers which can fire an interrupt each.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * OS (operating system) timer @ 32768 Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * DD (device driver) timer @ 1 kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * GP1 (general purpose 1) timer @ 1MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * GP2 (general purpose 2) timer @ 1MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /* Reset OS Timer 32bit (-/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define U300_TIMER_APP_ROST					(0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define U300_TIMER_APP_ROST_TIMER_RESET				(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /* Enable OS Timer 32bit (-/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define U300_TIMER_APP_EOST					(0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define U300_TIMER_APP_EOST_TIMER_ENABLE			(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) /* Disable OS Timer 32bit (-/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define U300_TIMER_APP_DOST					(0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define U300_TIMER_APP_DOST_TIMER_DISABLE			(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) /* OS Timer Mode Register 32bit (-/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define U300_TIMER_APP_SOSTM					(0x000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define U300_TIMER_APP_SOSTM_MODE_CONTINUOUS			(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define U300_TIMER_APP_SOSTM_MODE_ONE_SHOT			(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) /* OS Timer Status Register 32bit (R/-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define U300_TIMER_APP_OSTS					(0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define U300_TIMER_APP_OSTS_TIMER_STATE_MASK			(0x0000000F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define U300_TIMER_APP_OSTS_TIMER_STATE_IDLE			(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define U300_TIMER_APP_OSTS_TIMER_STATE_ACTIVE			(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define U300_TIMER_APP_OSTS_ENABLE_IND				(0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define U300_TIMER_APP_OSTS_MODE_MASK				(0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define U300_TIMER_APP_OSTS_MODE_CONTINUOUS			(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define U300_TIMER_APP_OSTS_MODE_ONE_SHOT			(0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define U300_TIMER_APP_OSTS_IRQ_ENABLED_IND			(0x00000040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define U300_TIMER_APP_OSTS_IRQ_PENDING_IND			(0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) /* OS Timer Current Count Register 32bit (R/-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define U300_TIMER_APP_OSTCC					(0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) /* OS Timer Terminal Count Register 32bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define U300_TIMER_APP_OSTTC					(0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) /* OS Timer Interrupt Enable Register 32bit (-/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define U300_TIMER_APP_OSTIE					(0x001c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define U300_TIMER_APP_OSTIE_IRQ_DISABLE			(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define U300_TIMER_APP_OSTIE_IRQ_ENABLE				(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) /* OS Timer Interrupt Acknowledge Register 32bit (-/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define U300_TIMER_APP_OSTIA					(0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define U300_TIMER_APP_OSTIA_IRQ_ACK				(0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) /* Reset DD Timer 32bit (-/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define U300_TIMER_APP_RDDT					(0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define U300_TIMER_APP_RDDT_TIMER_RESET				(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) /* Enable DD Timer 32bit (-/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define U300_TIMER_APP_EDDT					(0x0044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define U300_TIMER_APP_EDDT_TIMER_ENABLE			(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) /* Disable DD Timer 32bit (-/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define U300_TIMER_APP_DDDT					(0x0048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define U300_TIMER_APP_DDDT_TIMER_DISABLE			(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) /* DD Timer Mode Register 32bit (-/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define U300_TIMER_APP_SDDTM					(0x004c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define U300_TIMER_APP_SDDTM_MODE_CONTINUOUS			(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define U300_TIMER_APP_SDDTM_MODE_ONE_SHOT			(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) /* DD Timer Status Register 32bit (R/-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define U300_TIMER_APP_DDTS					(0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define U300_TIMER_APP_DDTS_TIMER_STATE_MASK			(0x0000000F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define U300_TIMER_APP_DDTS_TIMER_STATE_IDLE			(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define U300_TIMER_APP_DDTS_TIMER_STATE_ACTIVE			(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define U300_TIMER_APP_DDTS_ENABLE_IND				(0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define U300_TIMER_APP_DDTS_MODE_MASK				(0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define U300_TIMER_APP_DDTS_MODE_CONTINUOUS			(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define U300_TIMER_APP_DDTS_MODE_ONE_SHOT			(0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define U300_TIMER_APP_DDTS_IRQ_ENABLED_IND			(0x00000040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define U300_TIMER_APP_DDTS_IRQ_PENDING_IND			(0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) /* DD Timer Current Count Register 32bit (R/-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define U300_TIMER_APP_DDTCC					(0x0054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) /* DD Timer Terminal Count Register 32bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define U300_TIMER_APP_DDTTC					(0x0058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) /* DD Timer Interrupt Enable Register 32bit (-/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define U300_TIMER_APP_DDTIE					(0x005c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define U300_TIMER_APP_DDTIE_IRQ_DISABLE			(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define U300_TIMER_APP_DDTIE_IRQ_ENABLE				(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* DD Timer Interrupt Acknowledge Register 32bit (-/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define U300_TIMER_APP_DDTIA					(0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define U300_TIMER_APP_DDTIA_IRQ_ACK				(0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Reset GP1 Timer 32bit (-/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define U300_TIMER_APP_RGPT1					(0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define U300_TIMER_APP_RGPT1_TIMER_RESET			(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Enable GP1 Timer 32bit (-/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define U300_TIMER_APP_EGPT1					(0x0084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define U300_TIMER_APP_EGPT1_TIMER_ENABLE			(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Disable GP1 Timer 32bit (-/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define U300_TIMER_APP_DGPT1					(0x0088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define U300_TIMER_APP_DGPT1_TIMER_DISABLE			(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* GP1 Timer Mode Register 32bit (-/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define U300_TIMER_APP_SGPT1M					(0x008c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS			(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT			(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* GP1 Timer Status Register 32bit (R/-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define U300_TIMER_APP_GPT1S					(0x0090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define U300_TIMER_APP_GPT1S_TIMER_STATE_MASK			(0x0000000F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define U300_TIMER_APP_GPT1S_TIMER_STATE_IDLE			(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define U300_TIMER_APP_GPT1S_TIMER_STATE_ACTIVE			(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define U300_TIMER_APP_GPT1S_ENABLE_IND				(0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define U300_TIMER_APP_GPT1S_MODE_MASK				(0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define U300_TIMER_APP_GPT1S_MODE_CONTINUOUS			(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define U300_TIMER_APP_GPT1S_MODE_ONE_SHOT			(0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define U300_TIMER_APP_GPT1S_IRQ_ENABLED_IND			(0x00000040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define U300_TIMER_APP_GPT1S_IRQ_PENDING_IND			(0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* GP1 Timer Current Count Register 32bit (R/-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define U300_TIMER_APP_GPT1CC					(0x0094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* GP1 Timer Terminal Count Register 32bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define U300_TIMER_APP_GPT1TC					(0x0098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* GP1 Timer Interrupt Enable Register 32bit (-/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define U300_TIMER_APP_GPT1IE					(0x009c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define U300_TIMER_APP_GPT1IE_IRQ_DISABLE			(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define U300_TIMER_APP_GPT1IE_IRQ_ENABLE			(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* GP1 Timer Interrupt Acknowledge Register 32bit (-/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define U300_TIMER_APP_GPT1IA					(0x00a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define U300_TIMER_APP_GPT1IA_IRQ_ACK				(0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Reset GP2 Timer 32bit (-/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define U300_TIMER_APP_RGPT2					(0x00c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define U300_TIMER_APP_RGPT2_TIMER_RESET			(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Enable GP2 Timer 32bit (-/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define U300_TIMER_APP_EGPT2					(0x00c4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define U300_TIMER_APP_EGPT2_TIMER_ENABLE			(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Disable GP2 Timer 32bit (-/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define U300_TIMER_APP_DGPT2					(0x00c8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define U300_TIMER_APP_DGPT2_TIMER_DISABLE			(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* GP2 Timer Mode Register 32bit (-/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define U300_TIMER_APP_SGPT2M					(0x00cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS			(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define U300_TIMER_APP_SGPT2M_MODE_ONE_SHOT			(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* GP2 Timer Status Register 32bit (R/-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define U300_TIMER_APP_GPT2S					(0x00d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define U300_TIMER_APP_GPT2S_TIMER_STATE_MASK			(0x0000000F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define U300_TIMER_APP_GPT2S_TIMER_STATE_IDLE			(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define U300_TIMER_APP_GPT2S_TIMER_STATE_ACTIVE			(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define U300_TIMER_APP_GPT2S_ENABLE_IND				(0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define U300_TIMER_APP_GPT2S_MODE_MASK				(0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define U300_TIMER_APP_GPT2S_MODE_CONTINUOUS			(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define U300_TIMER_APP_GPT2S_MODE_ONE_SHOT			(0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define U300_TIMER_APP_GPT2S_IRQ_ENABLED_IND			(0x00000040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define U300_TIMER_APP_GPT2S_IRQ_PENDING_IND			(0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* GP2 Timer Current Count Register 32bit (R/-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define U300_TIMER_APP_GPT2CC					(0x00d4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* GP2 Timer Terminal Count Register 32bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define U300_TIMER_APP_GPT2TC					(0x00d8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* GP2 Timer Interrupt Enable Register 32bit (-/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define U300_TIMER_APP_GPT2IE					(0x00dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define U300_TIMER_APP_GPT2IE_IRQ_DISABLE			(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define U300_TIMER_APP_GPT2IE_IRQ_ENABLE			(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* GP2 Timer Interrupt Acknowledge Register 32bit (-/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define U300_TIMER_APP_GPT2IA					(0x00e0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define U300_TIMER_APP_GPT2IA_IRQ_ACK				(0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Clock request control register - all four timers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define U300_TIMER_APP_CRC					(0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE			(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static void __iomem *u300_timer_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct u300_clockevent_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	struct clock_event_device cevd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	unsigned ticks_per_jiffy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int u300_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	/* Disable interrupts on GP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	       u300_timer_base + U300_TIMER_APP_GPT1IE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	/* Disable GP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	       u300_timer_base + U300_TIMER_APP_DGPT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)  * If we have oneshot timer active, the oneshot scheduling function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)  * u300_set_next_event() is called immediately after.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int u300_set_oneshot(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	/* Just return; here? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	 * The actual event will be programmed by the next event hook,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	 * so we just set a dummy value somewhere at the end of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	 * universe here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	/* Disable interrupts on GPT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	       u300_timer_base + U300_TIMER_APP_GPT1IE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	/* Disable GP1 while we're reprogramming it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	       u300_timer_base + U300_TIMER_APP_DGPT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	 * Expire far in the future, u300_set_next_event() will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	 * called soon...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	writel(0xFFFFFFFF, u300_timer_base + U300_TIMER_APP_GPT1TC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	/* We run one shot per tick here! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	       u300_timer_base + U300_TIMER_APP_SGPT1M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	/* Enable interrupts for this timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	       u300_timer_base + U300_TIMER_APP_GPT1IE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	/* Enable timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	       u300_timer_base + U300_TIMER_APP_EGPT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static int u300_set_periodic(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	struct u300_clockevent_data *cevdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		container_of(evt, struct u300_clockevent_data, cevd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	/* Disable interrupts on GPT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	       u300_timer_base + U300_TIMER_APP_GPT1IE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	/* Disable GP1 while we're reprogramming it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	       u300_timer_base + U300_TIMER_APP_DGPT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	 * Set the periodic mode to a certain number of ticks per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	 * jiffy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	writel(cevdata->ticks_per_jiffy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	       u300_timer_base + U300_TIMER_APP_GPT1TC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	 * Set continuous mode, so the timer keeps triggering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	 * interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	       u300_timer_base + U300_TIMER_APP_SGPT1M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	/* Enable timer interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	       u300_timer_base + U300_TIMER_APP_GPT1IE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	/* Then enable the OS timer again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	       u300_timer_base + U300_TIMER_APP_EGPT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)  * The app timer in one shot mode obviously has to be reprogrammed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)  * in EXACTLY this sequence to work properly. Do NOT try to e.g. replace
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)  * the interrupt disable + timer disable commands with a reset command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)  * it will fail miserably. Apparently (and I found this the hard way)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)  * the timer is very sensitive to the instruction order, though you don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)  * get that impression from the data sheet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int u300_set_next_event(unsigned long cycles,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 			       struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	/* Disable interrupts on GPT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	       u300_timer_base + U300_TIMER_APP_GPT1IE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	/* Disable GP1 while we're reprogramming it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	       u300_timer_base + U300_TIMER_APP_DGPT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	/* Reset the General Purpose timer 1. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	       u300_timer_base + U300_TIMER_APP_RGPT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	/* IRQ in n * cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	writel(cycles, u300_timer_base + U300_TIMER_APP_GPT1TC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	 * We run one shot per tick here! (This is necessary to reconfigure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	 * the timer will tilt if you don't!)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	       u300_timer_base + U300_TIMER_APP_SGPT1M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	/* Enable timer interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	       u300_timer_base + U300_TIMER_APP_GPT1IE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	/* Then enable the OS timer again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	       u300_timer_base + U300_TIMER_APP_EGPT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static struct u300_clockevent_data u300_clockevent_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	/* Use general purpose timer 1 as clock event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	.cevd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		.name			= "GPT1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		/* Reasonably fast and accurate clock event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		.rating			= 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		.features		= CLOCK_EVT_FEAT_PERIODIC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 					  CLOCK_EVT_FEAT_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		.set_next_event		= u300_set_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		.set_state_shutdown	= u300_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		.set_state_periodic	= u300_set_periodic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		.set_state_oneshot	= u300_set_oneshot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* Clock event timer interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static irqreturn_t u300_timer_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	struct clock_event_device *evt = &u300_clockevent_data.cevd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	/* ACK/Clear timer IRQ for the APP GPT1 Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	writel(U300_TIMER_APP_GPT1IA_IRQ_ACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		u300_timer_base + U300_TIMER_APP_GPT1IA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	evt->event_handler(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)  * Override the global weak sched_clock symbol with this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)  * local implementation which uses the clocksource to get some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)  * better resolution when scheduling the kernel. We accept that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)  * this wraps around for now, since it is just a relative time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)  * stamp. (Inspired by OMAP implementation.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static u64 notrace u300_read_sched_clock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static unsigned long u300_read_current_timer(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static struct delay_timer u300_delay_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)  * This sets up the system timers, clock source and clock event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static int __init u300_timer_init_of(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	u300_timer_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	if (!u300_timer_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		pr_err("could not ioremap system timer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	/* Get the IRQ for the GP1 timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	irq = irq_of_parse_and_map(np, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	if (!irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		pr_err("no IRQ for system timer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	pr_info("U300 GP1 timer @ base: %p, IRQ: %u\n", u300_timer_base, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	/* Clock the interrupt controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	clk = of_clk_get(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	u300_clockevent_data.ticks_per_jiffy = DIV_ROUND_CLOSEST(rate, HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	sched_clock_register(u300_read_sched_clock, 32, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	u300_delay_timer.read_current_timer = &u300_read_current_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	u300_delay_timer.freq = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	register_current_timer_delay(&u300_delay_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	 * Disable the "OS" and "DD" timers - these are designed for Symbian!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	 * Example usage in cnh1601578 cpu subsystem pd_timer_app.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		u300_timer_base + U300_TIMER_APP_CRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	writel(U300_TIMER_APP_ROST_TIMER_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		u300_timer_base + U300_TIMER_APP_ROST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	writel(U300_TIMER_APP_DOST_TIMER_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		u300_timer_base + U300_TIMER_APP_DOST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	writel(U300_TIMER_APP_RDDT_TIMER_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 		u300_timer_base + U300_TIMER_APP_RDDT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	writel(U300_TIMER_APP_DDDT_TIMER_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		u300_timer_base + U300_TIMER_APP_DDDT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	/* Reset the General Purpose timer 1. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		u300_timer_base + U300_TIMER_APP_RGPT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	/* Set up the IRQ handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	ret = request_irq(irq, u300_timer_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 			  IRQF_TIMER | IRQF_IRQPOLL, "U300 Timer Tick", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	/* Reset the General Purpose timer 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	writel(U300_TIMER_APP_RGPT2_TIMER_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 		u300_timer_base + U300_TIMER_APP_RGPT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	/* Set this timer to run around forever */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	writel(0xFFFFFFFFU, u300_timer_base + U300_TIMER_APP_GPT2TC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	/* Set continuous mode so it wraps around */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	       u300_timer_base + U300_TIMER_APP_SGPT2M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	/* Disable timer interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 		u300_timer_base + U300_TIMER_APP_GPT2IE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	/* Then enable the GP2 timer to use as a free running us counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 		u300_timer_base + U300_TIMER_APP_EGPT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	/* Use general purpose timer 2 as clock source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	ret = clocksource_mmio_init(u300_timer_base + U300_TIMER_APP_GPT2CC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 				    "GPT2", rate, 300, 32, clocksource_mmio_readl_up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 		pr_err("timer: failed to initialize U300 clock source\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	/* Configure and register the clockevent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	clockevents_config_and_register(&u300_clockevent_data.cevd, rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 					1, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	 * TODO: init and register the rest of the timers too, they can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	 * used by hrtimers!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) TIMER_OF_DECLARE(u300_timer, "stericsson,u300-apptimer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 		       u300_timer_init_of);