^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/plat-omap/dmtimer.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * OMAP Dual-Mode Timers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Tarun Kanti DebBarma <tarun.kanti@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Thara Gopinath <thara@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * dmtimer adaptation to platform_driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Copyright (C) 2005 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * OMAP2 support by Juha Yrjola
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * API improvements and OMAP2 clock framework support by Timo Teras
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Copyright (C) 2009 Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/cpu_pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/platform_data/dmtimer-omap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <clocksource/timer-ti-dm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static u32 omap_reserved_systimers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static LIST_HEAD(omap_timer_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static DEFINE_SPINLOCK(dm_timer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) REQUEST_ANY = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) REQUEST_BY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) REQUEST_BY_CAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) REQUEST_BY_NODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * omap_dm_timer_read_reg - read timer registers in posted and non-posted mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @timer: timer pointer over which read operation to perform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @reg: lowest byte holds the register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * The posted mode bit is encoded in reg. Note that in posted mode write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * pending bit must be checked. Otherwise a read of a non completed write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * will produce an error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return __omap_dm_timer_read(timer, reg, timer->posted);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * omap_dm_timer_write_reg - write timer registers in posted and non-posted mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * @timer: timer pointer over which write operation is to perform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * @reg: lowest byte holds the register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * @value: data to write into the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * The posted mode bit is encoded in reg. Note that in posted mode the write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * pending bit must be checked. Otherwise a write on a register which has a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * pending write will be lost.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) __omap_dm_timer_write(timer, reg, value, timer->posted);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static void omap_timer_restore_context(struct omap_dm_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) __omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) timer->context.ocp_cfg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) timer->context.twer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) timer->context.tcrr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) timer->context.tldr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) timer->context.tmar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) timer->context.tsicr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) writel_relaxed(timer->context.tier, timer->irq_ena);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) timer->context.tclr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static void omap_timer_save_context(struct omap_dm_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) timer->context.ocp_cfg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) __omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) timer->context.tclr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) timer->context.twer =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) timer->context.tldr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) omap_dm_timer_read_reg(timer, OMAP_TIMER_LOAD_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) timer->context.tmar =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) omap_dm_timer_read_reg(timer, OMAP_TIMER_MATCH_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) timer->context.tier = readl_relaxed(timer->irq_ena);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) timer->context.tsicr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) omap_dm_timer_read_reg(timer, OMAP_TIMER_IF_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int omap_timer_context_notifier(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned long cmd, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct omap_dm_timer *timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) timer = container_of(nb, struct omap_dm_timer, nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) case CPU_CLUSTER_PM_ENTER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if ((timer->capability & OMAP_TIMER_ALWON) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) !atomic_read(&timer->enabled))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) omap_timer_save_context(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) case CPU_CLUSTER_PM_ENTER_FAILED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) case CPU_CLUSTER_PM_EXIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if ((timer->capability & OMAP_TIMER_ALWON) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) !atomic_read(&timer->enabled))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) omap_timer_restore_context(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int omap_dm_timer_reset(struct omap_dm_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 l, timeout = 100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (timer->revision != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) l = __omap_dm_timer_read(timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) OMAP_TIMER_V1_SYS_STAT_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) } while (!l && timeout--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (!timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) dev_err(&timer->pdev->dev, "Timer failed to reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* Configure timer for smart-idle mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) l = __omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) l |= 0x2 << 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) __omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) timer->posted = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct clk *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct dmtimer_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (unlikely(!timer) || IS_ERR(timer->fclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) switch (source) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) case OMAP_TIMER_SRC_SYS_CLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) parent_name = "timer_sys_ck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) case OMAP_TIMER_SRC_32_KHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) parent_name = "timer_32k_ck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) case OMAP_TIMER_SRC_EXT_CLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) parent_name = "timer_ext_ck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) pdata = timer->pdev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * FIXME: Used for OMAP1 devices only because they do not currently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * use the clock framework to set the parent clock. To be removed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * once OMAP1 migrated to using clock framework for dmtimers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (pdata && pdata->set_timer_src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return pdata->set_timer_src(timer->pdev, source);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #if defined(CONFIG_COMMON_CLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Check if the clock has configurable parents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (clk_hw_get_num_parents(__clk_get_hw(timer->fclk)) < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) parent = clk_get(&timer->pdev->dev, parent_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (IS_ERR(parent)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) pr_err("%s: %s not found\n", __func__, parent_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ret = clk_set_parent(timer->fclk, parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) pr_err("%s: failed to set %s as parent\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) parent_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) clk_put(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static void omap_dm_timer_enable(struct omap_dm_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) pm_runtime_get_sync(&timer->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static void omap_dm_timer_disable(struct omap_dm_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) pm_runtime_put_sync(&timer->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int omap_dm_timer_prepare(struct omap_dm_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * FIXME: OMAP1 devices do not use the clock framework for dmtimers so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * do not call clk_get() for these devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) timer->fclk = clk_get(&timer->pdev->dev, "fck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (WARN_ON_ONCE(IS_ERR(timer->fclk))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) dev_err(&timer->pdev->dev, ": No fclk handle.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) omap_dm_timer_enable(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (timer->capability & OMAP_TIMER_NEEDS_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) rc = omap_dm_timer_reset(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) omap_dm_timer_disable(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) __omap_dm_timer_enable_posted(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) omap_dm_timer_disable(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static inline u32 omap_dm_timer_reserved_systimer(int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int omap_dm_timer_reserve_systimer(int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (omap_dm_timer_reserved_systimer(id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) omap_reserved_systimers |= (1 << (id - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static struct omap_dm_timer *_omap_dm_timer_request(int req_type, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct omap_dm_timer *timer = NULL, *t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct device_node *np = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u32 cap = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) switch (req_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) case REQUEST_BY_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) id = *(int *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) case REQUEST_BY_CAP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) cap = *(u32 *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) case REQUEST_BY_NODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) np = (struct device_node *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* REQUEST_ANY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) spin_lock_irqsave(&dm_timer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) list_for_each_entry(t, &omap_timer_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (t->reserved)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) switch (req_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) case REQUEST_BY_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (id == t->pdev->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) timer = t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) timer->reserved = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) goto found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) case REQUEST_BY_CAP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (cap == (t->capability & cap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * If timer is not NULL, we have already found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * one timer. But it was not an exact match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * because it had more capabilities than what
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * was required. Therefore, unreserve the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * timer found and see if this one is a better
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * match.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) timer->reserved = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) timer = t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) timer->reserved = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* Exit loop early if we find an exact match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (t->capability == cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) goto found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) case REQUEST_BY_NODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (np == t->pdev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) timer = t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) timer->reserved = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) goto found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* REQUEST_ANY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) timer = t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) timer->reserved = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) goto found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) found:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) spin_unlock_irqrestore(&dm_timer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (timer && omap_dm_timer_prepare(timer)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) timer->reserved = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) timer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (!timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) pr_debug("%s: timer request failed!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static struct omap_dm_timer *omap_dm_timer_request(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return _omap_dm_timer_request(REQUEST_ANY, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static struct omap_dm_timer *omap_dm_timer_request_specific(int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* Requesting timer by ID is not supported when device tree is used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (of_have_populated_dt()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) pr_warn("%s: Please use omap_dm_timer_request_by_node()\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return _omap_dm_timer_request(REQUEST_BY_ID, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * omap_dm_timer_request_by_cap - Request a timer by capability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * @cap: Bit mask of capabilities to match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * Find a timer based upon capabilities bit mask. Callers of this function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * should use the definitions found in the plat/dmtimer.h file under the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * comment "timer capabilities used in hwmod database". Returns pointer to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * timer handle on success and a NULL pointer on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return _omap_dm_timer_request(REQUEST_BY_CAP, &cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * omap_dm_timer_request_by_node - Request a timer by device-tree node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * @np: Pointer to device-tree timer node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * Request a timer based upon a device node pointer. Returns pointer to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * timer handle on success and a NULL pointer on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static struct omap_dm_timer *omap_dm_timer_request_by_node(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return _omap_dm_timer_request(REQUEST_BY_NODE, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static int omap_dm_timer_free(struct omap_dm_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (unlikely(!timer))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) clk_put(timer->fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) WARN_ON(!timer->reserved);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) timer->reserved = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return timer->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #if defined(CONFIG_ARCH_OMAP1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * @inputmask: current value of idlect mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct omap_dm_timer *timer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* If ARMXOR cannot be idled this function call is unnecessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (!(inputmask & (1 << 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return inputmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* If any active timer is using ARMXOR return modified mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) spin_lock_irqsave(&dm_timer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) list_for_each_entry(timer, &omap_timer_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (l & OMAP_TIMER_CTRL_ST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) inputmask &= ~(1 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) inputmask &= ~(1 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) spin_unlock_irqrestore(&dm_timer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return inputmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (timer && !IS_ERR(timer->fclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return timer->fclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) int omap_dm_timer_trigger(struct omap_dm_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (unlikely(!timer || !atomic_read(&timer->enabled))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) pr_err("%s: timer not available or enabled.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static int omap_dm_timer_start(struct omap_dm_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (unlikely(!timer))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) omap_dm_timer_enable(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (!(l & OMAP_TIMER_CTRL_ST)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) l |= OMAP_TIMER_CTRL_ST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static int omap_dm_timer_stop(struct omap_dm_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) unsigned long rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (unlikely(!timer))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (!(timer->capability & OMAP_TIMER_NEEDS_RESET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) rate = clk_get_rate(timer->fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) __omap_dm_timer_stop(timer, timer->posted, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) omap_dm_timer_disable(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static int omap_dm_timer_set_load(struct omap_dm_timer *timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) unsigned int load)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (unlikely(!timer))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) omap_dm_timer_enable(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) omap_dm_timer_disable(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) unsigned int match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (unlikely(!timer))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) omap_dm_timer_enable(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) l |= OMAP_TIMER_CTRL_CE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) l &= ~OMAP_TIMER_CTRL_CE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) omap_dm_timer_disable(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) int toggle, int trigger, int autoreload)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (unlikely(!timer))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) omap_dm_timer_enable(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) OMAP_TIMER_CTRL_PT | (0x03 << 10) | OMAP_TIMER_CTRL_AR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (def_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) l |= OMAP_TIMER_CTRL_SCPWM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (toggle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) l |= OMAP_TIMER_CTRL_PT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) l |= trigger << 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (autoreload)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) l |= OMAP_TIMER_CTRL_AR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) omap_dm_timer_disable(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static int omap_dm_timer_get_pwm_status(struct omap_dm_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (unlikely(!timer))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) omap_dm_timer_enable(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) omap_dm_timer_disable(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) int prescaler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (unlikely(!timer) || prescaler < -1 || prescaler > 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) omap_dm_timer_enable(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (prescaler >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) l |= OMAP_TIMER_CTRL_PRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) l |= prescaler << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) omap_dm_timer_disable(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) unsigned int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (unlikely(!timer))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) omap_dm_timer_enable(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) __omap_dm_timer_int_enable(timer, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) omap_dm_timer_disable(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * omap_dm_timer_set_int_disable - disable timer interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * @timer: pointer to timer handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * @mask: bit mask of interrupts to be disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * Disables the specified timer interrupts for a timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) u32 l = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (unlikely(!timer))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) omap_dm_timer_enable(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (timer->revision == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) l = readl_relaxed(timer->irq_ena) & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) writel_relaxed(l, timer->irq_dis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) omap_dm_timer_disable(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) unsigned int l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (unlikely(!timer || !atomic_read(&timer->enabled))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) pr_err("%s: timer not available or enabled.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) l = readl_relaxed(timer->irq_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (unlikely(!timer || !atomic_read(&timer->enabled)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) __omap_dm_timer_write_status(timer, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (unlikely(!timer || !atomic_read(&timer->enabled))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) pr_err("%s: timer not iavailable or enabled.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return __omap_dm_timer_read_counter(timer, timer->posted);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (unlikely(!timer || !atomic_read(&timer->enabled))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) pr_err("%s: timer not available or enabled.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /* Save the context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) timer->context.tcrr = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) int omap_dm_timers_active(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) struct omap_dm_timer *timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) list_for_each_entry(timer, &omap_timer_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (!timer->reserved)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) OMAP_TIMER_CTRL_ST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static int __maybe_unused omap_dm_timer_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) struct omap_dm_timer *timer = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) atomic_set(&timer->enabled, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (timer->capability & OMAP_TIMER_ALWON || !timer->func_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) omap_timer_save_context(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static int __maybe_unused omap_dm_timer_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) struct omap_dm_timer *timer = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (!(timer->capability & OMAP_TIMER_ALWON) && timer->func_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) omap_timer_restore_context(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) atomic_set(&timer->enabled, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static const struct dev_pm_ops omap_dm_timer_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) SET_RUNTIME_PM_OPS(omap_dm_timer_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) omap_dm_timer_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static const struct of_device_id omap_timer_match[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) * omap_dm_timer_probe - probe function called for every registered device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) * @pdev: pointer to current timer platform device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * Called by driver framework at the end of device registration for all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * timer devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static int omap_dm_timer_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) struct omap_dm_timer *timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) const struct dmtimer_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) pdata = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) dev->platform_data = (void *)pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) dev_err(dev, "%s: no platform data.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) timer = devm_kzalloc(dev, sizeof(*timer), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (!timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) timer->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (timer->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return timer->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) timer->fclk = ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) timer->io_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (IS_ERR(timer->io_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) return PTR_ERR(timer->io_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) platform_set_drvdata(pdev, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (dev->of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (of_find_property(dev->of_node, "ti,timer-alwon", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) timer->capability |= OMAP_TIMER_ALWON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (of_find_property(dev->of_node, "ti,timer-dsp", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) timer->capability |= OMAP_TIMER_HAS_DSP_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (of_find_property(dev->of_node, "ti,timer-pwm", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) timer->capability |= OMAP_TIMER_HAS_PWM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (of_find_property(dev->of_node, "ti,timer-secure", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) timer->capability |= OMAP_TIMER_SECURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) timer->id = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) timer->capability = pdata->timer_capability;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) timer->reserved = omap_dm_timer_reserved_systimer(timer->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (!(timer->capability & OMAP_TIMER_ALWON)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) timer->nb.notifier_call = omap_timer_context_notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) cpu_pm_register_notifier(&timer->nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) timer->errata = pdata->timer_errata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) timer->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (!timer->reserved) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) ret = pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) dev_err(dev, "%s: pm_runtime_get_sync failed!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) goto err_get_sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) __omap_dm_timer_init_regs(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) pm_runtime_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) /* add the timer element to the list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) spin_lock_irqsave(&dm_timer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) list_add_tail(&timer->node, &omap_timer_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) spin_unlock_irqrestore(&dm_timer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) dev_dbg(dev, "Device Probed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) err_get_sync:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) pm_runtime_put_noidle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) * omap_dm_timer_remove - cleanup a registered timer device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) * @pdev: pointer to current timer platform device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) * Called by driver framework whenever a timer device is unregistered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) * In addition to freeing platform resources it also deletes the timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) * entry from the local list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) static int omap_dm_timer_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) struct omap_dm_timer *timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) spin_lock_irqsave(&dm_timer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) list_for_each_entry(timer, &omap_timer_list, node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (!strcmp(dev_name(&timer->pdev->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) dev_name(&pdev->dev))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (!(timer->capability & OMAP_TIMER_ALWON))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) cpu_pm_unregister_notifier(&timer->nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) list_del(&timer->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) spin_unlock_irqrestore(&dm_timer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) static const struct omap_dm_timer_ops dmtimer_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .request_by_node = omap_dm_timer_request_by_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .request_specific = omap_dm_timer_request_specific,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .request = omap_dm_timer_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .set_source = omap_dm_timer_set_source,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .get_irq = omap_dm_timer_get_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .set_int_enable = omap_dm_timer_set_int_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .set_int_disable = omap_dm_timer_set_int_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .free = omap_dm_timer_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .enable = omap_dm_timer_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .disable = omap_dm_timer_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .get_fclk = omap_dm_timer_get_fclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .start = omap_dm_timer_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .stop = omap_dm_timer_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .set_load = omap_dm_timer_set_load,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .set_match = omap_dm_timer_set_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .set_pwm = omap_dm_timer_set_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .get_pwm_status = omap_dm_timer_get_pwm_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .set_prescaler = omap_dm_timer_set_prescaler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .read_counter = omap_dm_timer_read_counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .write_counter = omap_dm_timer_write_counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .read_status = omap_dm_timer_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .write_status = omap_dm_timer_write_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) static const struct dmtimer_platform_data omap3plus_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .timer_errata = OMAP_TIMER_ERRATA_I103_I767,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .timer_ops = &dmtimer_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static const struct of_device_id omap_timer_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .compatible = "ti,omap2420-timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .compatible = "ti,omap3430-timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .data = &omap3plus_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .compatible = "ti,omap4430-timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .data = &omap3plus_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .compatible = "ti,omap5430-timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .data = &omap3plus_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .compatible = "ti,am335x-timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .data = &omap3plus_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .compatible = "ti,am335x-timer-1ms",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .data = &omap3plus_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .compatible = "ti,dm816-timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .data = &omap3plus_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) MODULE_DEVICE_TABLE(of, omap_timer_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static struct platform_driver omap_dm_timer_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .probe = omap_dm_timer_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .remove = omap_dm_timer_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .name = "omap_timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .of_match_table = of_match_ptr(omap_timer_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .pm = &omap_dm_timer_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) module_platform_driver(omap_dm_timer_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) MODULE_AUTHOR("Texas Instruments Inc");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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