^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/cpuhotplug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk/clk-conf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <clocksource/timer-ti-dm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <dt-bindings/bus/ti-sysc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* For type1, set SYSC_OMAP2_CLOCKACTIVITY for fck off on idle, l4 clock on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DMTIMER_TYPE1_ENABLE ((1 << 9) | (SYSC_IDLE_SMART << 3) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_AUTOIDLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DMTIMER_TYPE1_DISABLE (SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DMTIMER_TYPE2_ENABLE (SYSC_IDLE_SMART_WKUP << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DMTIMER_RESET_WAIT 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DMTIMER_INST_DONT_CARE ~0U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static int counter_32k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static u32 clocksource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static u32 clockevent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * Subset of the timer registers we use. Note that the register offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * depend on the timer revision detected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct dmtimer_systimer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u8 sysc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u8 irq_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u8 irq_ena;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u8 pend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u8 load;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u8 counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u8 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u8 wakeup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u8 ifctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct clk *fck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct clk *ick;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct dmtimer_clockevent {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct clock_event_device dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct dmtimer_systimer t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct dmtimer_clocksource {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct clocksource dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct dmtimer_systimer t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int loadval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Assumes v1 ip if bits [31:16] are zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static bool dmtimer_systimer_revision1(struct dmtimer_systimer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 tidr = readl_relaxed(t->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return !(tidr >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static void dmtimer_systimer_enable(struct dmtimer_systimer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (dmtimer_systimer_revision1(t))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) val = DMTIMER_TYPE1_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) val = DMTIMER_TYPE2_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) writel_relaxed(val, t->base + t->sysc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static void dmtimer_systimer_disable(struct dmtimer_systimer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (!dmtimer_systimer_revision1(t))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) writel_relaxed(DMTIMER_TYPE1_DISABLE, t->base + t->sysc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static int __init dmtimer_systimer_type1_reset(struct dmtimer_systimer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) void __iomem *syss = t->base + OMAP_TIMER_V1_SYS_STAT_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) dmtimer_systimer_enable(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) writel_relaxed(BIT(1) | BIT(2), t->base + t->ifctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ret = readl_poll_timeout_atomic(syss, l, l & BIT(0), 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) DMTIMER_RESET_WAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Note we must use io_base instead of func_base for type2 OCP regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int __init dmtimer_systimer_type2_reset(struct dmtimer_systimer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) void __iomem *sysc = t->base + t->sysc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) dmtimer_systimer_enable(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) l = readl_relaxed(sysc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) l |= BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) writel_relaxed(l, sysc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return readl_poll_timeout_atomic(sysc, l, !(l & BIT(0)), 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) DMTIMER_RESET_WAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int __init dmtimer_systimer_reset(struct dmtimer_systimer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (dmtimer_systimer_revision1(t))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ret = dmtimer_systimer_type1_reset(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ret = dmtimer_systimer_type2_reset(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) pr_err("%s failed with %i\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static const struct of_device_id counter_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { .compatible = "ti,omap-counter32k" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { /* Sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * Check if the SoC als has a usable working 32 KiHz counter. The 32 KiHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * counter is handled by timer-ti-32k, but we need to detect it as it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * affects the preferred dmtimer system timer configuration. There is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * typically no use for a dmtimer clocksource if the 32 KiHz counter is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * present, except on am437x as described below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static void __init dmtimer_systimer_check_counter32k(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (counter_32k)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) np = of_find_matching_node(NULL, counter_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) counter_32k = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (of_device_is_available(np))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) counter_32k = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) counter_32k = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static const struct of_device_id dmtimer_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { .compatible = "ti,omap2420-timer", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { .compatible = "ti,omap3430-timer", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { .compatible = "ti,omap4430-timer", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { .compatible = "ti,omap5430-timer", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { .compatible = "ti,am335x-timer", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { .compatible = "ti,am335x-timer-1ms", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { .compatible = "ti,dm814-timer", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { .compatible = "ti,dm816-timer", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { /* Sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * Checks that system timers are configured to not reset and idle during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * the generic timer-ti-dm device driver probe. And that the system timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * source clocks are properly configured. Also, let's not hog any DSP and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * PWM capable timers unnecessarily as system timers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static bool __init dmtimer_is_preferred(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (!of_device_is_available(np))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (!of_property_read_bool(np->parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) "ti,no-reset-on-init"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (!of_property_read_bool(np->parent, "ti,no-idle"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Secure gptimer12 is always clocked with a fixed source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (!of_property_read_bool(np, "ti,timer-secure")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (!of_property_read_bool(np, "assigned-clocks"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (!of_property_read_bool(np, "assigned-clock-parents"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (of_property_read_bool(np, "ti,timer-dsp"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (of_property_read_bool(np, "ti,timer-pwm"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * Finds the first available usable always-on timer, and assigns it to either
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * clockevent or clocksource depending if the counter_32k is available on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * SoC or not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * Some omap3 boards with unreliable oscillator must not use the counter_32k
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * or dmtimer1 with 32 KiHz source. Additionally, the boards with unreliable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * oscillator should really set counter_32k as disabled, and delete dmtimer1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * ti,always-on property, but let's not count on it. For these quirky cases,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * we prefer using the always-on secure dmtimer12 with the internal 32 KiHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * clock as the clocksource, and any available dmtimer as clockevent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * For am437x, we are using am335x style dmtimer clocksource. It is unclear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * if this quirk handling is really needed, but let's change it separately
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * based on testing as it might cause side effects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static void __init dmtimer_systimer_assign_alwon(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u32 pa = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) bool quirk_unreliable_oscillator = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* Quirk unreliable 32 KiHz oscillator with incomplete dts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (of_machine_is_compatible("ti,omap3-beagle-ab4")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) quirk_unreliable_oscillator = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) counter_32k = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* Quirk am437x using am335x style dmtimer clocksource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (of_machine_is_compatible("ti,am43"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) counter_32k = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) for_each_matching_node(np, dmtimer_match_table) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (!dmtimer_is_preferred(np))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (of_property_read_bool(np, "ti,timer-alwon")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) const __be32 *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) addr = of_get_address(np, 0, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) pa = of_translate_address(np, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (pa) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Quirky omap3 boards must use dmtimer12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (quirk_unreliable_oscillator &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) pa == 0x48318000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* Usually no need for dmtimer clocksource if we have counter32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (counter_32k >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) clockevent = pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) clocksource = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) clocksource = pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) clockevent = DMTIMER_INST_DONT_CARE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* Finds the first usable dmtimer, used for the don't care case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static u32 __init dmtimer_systimer_find_first_available(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) const __be32 *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u32 pa = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) for_each_matching_node(np, dmtimer_match_table) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (!dmtimer_is_preferred(np))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) addr = of_get_address(np, 0, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) pa = of_translate_address(np, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (pa) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (pa == clocksource || pa == clockevent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) pa = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* Selects the best clocksource and clockevent to use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static void __init dmtimer_systimer_select_best(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) dmtimer_systimer_check_counter32k();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) dmtimer_systimer_assign_alwon();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (clockevent == DMTIMER_INST_DONT_CARE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) clockevent = dmtimer_systimer_find_first_available();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) pr_debug("%s: counter_32k: %i clocksource: %08x clockevent: %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) __func__, counter_32k, clocksource, clockevent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* Interface clocks are only available on some SoCs variants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int __init dmtimer_systimer_init_clock(struct dmtimer_systimer *t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) unsigned long *rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct clk *clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) unsigned long r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) bool is_ick = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) is_ick = !strncmp(name, "ick", 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) clock = of_clk_get_by_name(np, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if ((PTR_ERR(clock) == -EINVAL) && is_ick)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) else if (IS_ERR(clock))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return PTR_ERR(clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) error = clk_prepare_enable(clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) r = clk_get_rate(clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (!r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (is_ick)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) t->ick = clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) t->fck = clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) *rate = r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int __init dmtimer_systimer_setup(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct dmtimer_systimer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u8 regbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (!of_device_is_compatible(np->parent, "ti,sysc"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) t->base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (!t->base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * Enable optional assigned-clock-parents configured at the timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * node level. For regular device drivers, this is done automatically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * by bus related code such as platform_drv_probe().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) error = of_clk_set_defaults(np, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (error < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) pr_err("%s: clock source init failed: %i\n", __func__, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* For ti-sysc, we have timer clocks at the parent module level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) error = dmtimer_systimer_init_clock(t, np->parent, "fck", &rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) goto err_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) t->rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) error = dmtimer_systimer_init_clock(t, np->parent, "ick", &rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) goto err_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (dmtimer_systimer_revision1(t)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) t->irq_stat = OMAP_TIMER_V1_STAT_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) t->irq_ena = OMAP_TIMER_V1_INT_EN_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) t->pend = _OMAP_TIMER_WRITE_PEND_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) regbase = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) t->irq_stat = OMAP_TIMER_V2_IRQSTATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) t->irq_ena = OMAP_TIMER_V2_IRQENABLE_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) regbase = OMAP_TIMER_V2_FUNC_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) t->pend = regbase + _OMAP_TIMER_WRITE_PEND_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) t->sysc = OMAP_TIMER_OCP_CFG_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) t->load = regbase + _OMAP_TIMER_LOAD_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) t->counter = regbase + _OMAP_TIMER_COUNTER_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) t->ctrl = regbase + _OMAP_TIMER_CTRL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) t->wakeup = regbase + _OMAP_TIMER_WAKEUP_EN_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) t->ifctrl = regbase + _OMAP_TIMER_IF_CTRL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) dmtimer_systimer_reset(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) dmtimer_systimer_enable(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) pr_debug("dmtimer rev %08x sysc %08x\n", readl_relaxed(t->base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) readl_relaxed(t->base + t->sysc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) err_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) iounmap(t->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* Clockevent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static struct dmtimer_clockevent *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) to_dmtimer_clockevent(struct clock_event_device *clockevent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return container_of(clockevent, struct dmtimer_clockevent, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static irqreturn_t dmtimer_clockevent_interrupt(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct dmtimer_clockevent *clkevt = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct dmtimer_systimer *t = &clkevt->t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) clkevt->dev.event_handler(&clkevt->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static int dmtimer_set_next_event(unsigned long cycles,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct dmtimer_clockevent *clkevt = to_dmtimer_clockevent(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct dmtimer_systimer *t = &clkevt->t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) void __iomem *pend = t->base + t->pend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) while (readl_relaxed(pend) & WP_TCRR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) writel_relaxed(0xffffffff - cycles, t->base + t->counter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) while (readl_relaxed(pend) & WP_TCLR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) writel_relaxed(OMAP_TIMER_CTRL_ST, t->base + t->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static int dmtimer_clockevent_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct dmtimer_clockevent *clkevt = to_dmtimer_clockevent(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct dmtimer_systimer *t = &clkevt->t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) void __iomem *ctrl = t->base + t->ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) l = readl_relaxed(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (l & OMAP_TIMER_CTRL_ST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) l &= ~BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) writel_relaxed(l, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* Flush posted write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) l = readl_relaxed(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* Wait for functional clock period x 3.5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) udelay(3500000 / t->rate + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static int dmtimer_set_periodic(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct dmtimer_clockevent *clkevt = to_dmtimer_clockevent(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct dmtimer_systimer *t = &clkevt->t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) void __iomem *pend = t->base + t->pend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) dmtimer_clockevent_shutdown(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* Looks like we need to first set the load value separately */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) while (readl_relaxed(pend) & WP_TLDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) writel_relaxed(clkevt->period, t->base + t->load);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) while (readl_relaxed(pend) & WP_TCRR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) writel_relaxed(clkevt->period, t->base + t->counter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) while (readl_relaxed(pend) & WP_TCLR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) writel_relaxed(OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) t->base + t->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static void omap_clockevent_idle(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct dmtimer_clockevent *clkevt = to_dmtimer_clockevent(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct dmtimer_systimer *t = &clkevt->t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) dmtimer_systimer_disable(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) clk_disable(t->fck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static void omap_clockevent_unidle(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct dmtimer_clockevent *clkevt = to_dmtimer_clockevent(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct dmtimer_systimer *t = &clkevt->t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) error = clk_enable(t->fck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) pr_err("could not enable timer fck on resume: %i\n", error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) dmtimer_systimer_enable(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_ena);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->wakeup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static int __init dmtimer_clkevt_init_common(struct dmtimer_clockevent *clkevt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) unsigned int features,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) const struct cpumask *cpumask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) int rating)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct clock_event_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct dmtimer_systimer *t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) t = &clkevt->t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) dev = &clkevt->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * We mostly use cpuidle_coupled with ARM local timers for runtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * so there's probably no use for CLOCK_EVT_FEAT_DYNIRQ here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) dev->features = features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) dev->rating = rating;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) dev->set_next_event = dmtimer_set_next_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) dev->set_state_shutdown = dmtimer_clockevent_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) dev->set_state_periodic = dmtimer_set_periodic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) dev->set_state_oneshot = dmtimer_clockevent_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) dev->set_state_oneshot_stopped = dmtimer_clockevent_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) dev->tick_resume = dmtimer_clockevent_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) dev->cpumask = cpumask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) dev->irq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (!dev->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) error = dmtimer_systimer_setup(np, &clkevt->t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) clkevt->period = 0xffffffff - DIV_ROUND_CLOSEST(t->rate, HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * For clock-event timers we never read the timer counter and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * so we are not impacted by errata i103 and i767. Therefore,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * we can safely ignore this errata for clock-event timers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) writel_relaxed(OMAP_TIMER_CTRL_POSTED, t->base + t->ifctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) error = request_irq(dev->irq, dmtimer_clockevent_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) IRQF_TIMER, name, clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) goto err_out_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_ena);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->wakeup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) pr_info("TI gptimer %s: %s%lu Hz at %pOF\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) name, of_find_property(np, "ti,timer-alwon", NULL) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) "always-on " : "", t->rate, np->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) err_out_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) iounmap(t->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static int __init dmtimer_clockevent_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct dmtimer_clockevent *clkevt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) clkevt = kzalloc(sizeof(*clkevt), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (!clkevt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) error = dmtimer_clkevt_init_common(clkevt, np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) CLOCK_EVT_FEAT_PERIODIC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) CLOCK_EVT_FEAT_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) cpu_possible_mask, "clockevent",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) goto err_out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) clockevents_config_and_register(&clkevt->dev, clkevt->t.rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 3, /* Timer internal resync latency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (of_machine_is_compatible("ti,am33xx") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) of_machine_is_compatible("ti,am43")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) clkevt->dev.suspend = omap_clockevent_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) clkevt->dev.resume = omap_clockevent_unidle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) err_out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) kfree(clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* Dmtimer as percpu timer. See dra7 ARM architected timer wrap erratum i940 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static DEFINE_PER_CPU(struct dmtimer_clockevent, dmtimer_percpu_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static int __init dmtimer_percpu_timer_init(struct device_node *np, int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct dmtimer_clockevent *clkevt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (!cpu_possible(cpu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (!of_property_read_bool(np->parent, "ti,no-reset-on-init") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) !of_property_read_bool(np->parent, "ti,no-idle"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) pr_warn("Incomplete dtb for percpu dmtimer %pOF\n", np->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) clkevt = per_cpu_ptr(&dmtimer_percpu_timer, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) error = dmtimer_clkevt_init_common(clkevt, np, CLOCK_EVT_FEAT_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) cpumask_of(cpu), "percpu-dmtimer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* See TRM for timer internal resynch latency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static int omap_dmtimer_starting_cpu(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) struct dmtimer_clockevent *clkevt = per_cpu_ptr(&dmtimer_percpu_timer, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct clock_event_device *dev = &clkevt->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) struct dmtimer_systimer *t = &clkevt->t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) clockevents_config_and_register(dev, t->rate, 3, ULONG_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) irq_force_affinity(dev->irq, cpumask_of(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static int __init dmtimer_percpu_timer_startup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct dmtimer_clockevent *clkevt = per_cpu_ptr(&dmtimer_percpu_timer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) struct dmtimer_systimer *t = &clkevt->t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (t->sysc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) cpuhp_setup_state(CPUHP_AP_TI_GP_TIMER_STARTING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) "clockevents/omap/gptimer:starting",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) omap_dmtimer_starting_cpu, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) subsys_initcall(dmtimer_percpu_timer_startup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static int __init dmtimer_percpu_quirk_init(struct device_node *np, u32 pa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) struct device_node *arm_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) arm_timer = of_find_compatible_node(NULL, NULL, "arm,armv7-timer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (of_device_is_available(arm_timer)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) pr_warn_once("ARM architected timer wrap issue i940 detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (pa == 0x4882c000) /* dra7 dmtimer15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return dmtimer_percpu_timer_init(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) else if (pa == 0x4882e000) /* dra7 dmtimer16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return dmtimer_percpu_timer_init(np, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /* Clocksource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static struct dmtimer_clocksource *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) to_dmtimer_clocksource(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return container_of(cs, struct dmtimer_clocksource, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static u64 dmtimer_clocksource_read_cycles(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct dmtimer_clocksource *clksrc = to_dmtimer_clocksource(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct dmtimer_systimer *t = &clksrc->t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return (u64)readl_relaxed(t->base + t->counter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static void __iomem *dmtimer_sched_clock_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static u64 notrace dmtimer_read_sched_clock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return readl_relaxed(dmtimer_sched_clock_counter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static void dmtimer_clocksource_suspend(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) struct dmtimer_clocksource *clksrc = to_dmtimer_clocksource(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) struct dmtimer_systimer *t = &clksrc->t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) clksrc->loadval = readl_relaxed(t->base + t->counter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) dmtimer_systimer_disable(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) clk_disable(t->fck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static void dmtimer_clocksource_resume(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) struct dmtimer_clocksource *clksrc = to_dmtimer_clocksource(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) struct dmtimer_systimer *t = &clksrc->t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) error = clk_enable(t->fck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) pr_err("could not enable timer fck on resume: %i\n", error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) dmtimer_systimer_enable(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) writel_relaxed(clksrc->loadval, t->base + t->counter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) writel_relaxed(OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) t->base + t->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static int __init dmtimer_clocksource_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct dmtimer_clocksource *clksrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) struct dmtimer_systimer *t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) struct clocksource *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) clksrc = kzalloc(sizeof(*clksrc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (!clksrc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) dev = &clksrc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) t = &clksrc->t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) error = dmtimer_systimer_setup(np, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) goto err_out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) dev->name = "dmtimer";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) dev->rating = 300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) dev->read = dmtimer_clocksource_read_cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) dev->mask = CLOCKSOURCE_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) dev->flags = CLOCK_SOURCE_IS_CONTINUOUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /* Unlike for clockevent, legacy code sets suspend only for am4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (of_machine_is_compatible("ti,am43")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) dev->suspend = dmtimer_clocksource_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) dev->resume = dmtimer_clocksource_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) writel_relaxed(0, t->base + t->counter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) writel_relaxed(OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) t->base + t->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) pr_info("TI gptimer clocksource: %s%pOF\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) of_find_property(np, "ti,timer-alwon", NULL) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) "always-on " : "", np->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (!dmtimer_sched_clock_counter) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) dmtimer_sched_clock_counter = t->base + t->counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) sched_clock_register(dmtimer_read_sched_clock, 32, t->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (clocksource_register_hz(dev, t->rate))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) pr_err("Could not register clocksource %pOF\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) err_out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) kfree(clksrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) * To detect between a clocksource and clockevent, we assume the device tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) * has no interrupts configured for a clocksource timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static int __init dmtimer_systimer_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) const __be32 *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) u32 pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /* One time init for the preferred timer configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (!clocksource && !clockevent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) dmtimer_systimer_select_best();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (!clocksource && !clockevent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) pr_err("%s: unable to detect system timers, update dtb?\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) addr = of_get_address(np, 0, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) pa = of_translate_address(np, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (!pa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (counter_32k <= 0 && clocksource == pa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return dmtimer_clocksource_init(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (clockevent == pa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return dmtimer_clockevent_init(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (of_machine_is_compatible("ti,dra7"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) return dmtimer_percpu_quirk_init(np, pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) TIMER_OF_DECLARE(systimer_omap2, "ti,omap2420-timer", dmtimer_systimer_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) TIMER_OF_DECLARE(systimer_omap3, "ti,omap3430-timer", dmtimer_systimer_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) TIMER_OF_DECLARE(systimer_omap4, "ti,omap4430-timer", dmtimer_systimer_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) TIMER_OF_DECLARE(systimer_omap5, "ti,omap5430-timer", dmtimer_systimer_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) TIMER_OF_DECLARE(systimer_am33x, "ti,am335x-timer", dmtimer_systimer_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) TIMER_OF_DECLARE(systimer_am3ms, "ti,am335x-timer-1ms", dmtimer_systimer_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) TIMER_OF_DECLARE(systimer_dm814, "ti,dm814-timer", dmtimer_systimer_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) TIMER_OF_DECLARE(systimer_dm816, "ti,dm816-timer", dmtimer_systimer_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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