^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * timer-ti-32k.c - OMAP2 32k Timer Support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Update to use new clocksource/clockevent layers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2007 MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Original driver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 2005 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Author: Paul Mundt <paul.mundt@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Juha Yrjölä <juha.yrjola@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * OMAP Dual-mode timer framework support by Timo Teras
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Some parts based off of TI's 24xx code:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Copyright (C) 2004-2009 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Roughly modelled after the OMAP1 MPU timer code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * 32KHz clocksource ... always available, on pretty most chips except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * OMAP 730 and 1510. Other timers could be used as clocksources, with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * higher resolution in free-running counter modes (e.g. 12 MHz xtal),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * but systems won't necessarily want to spend resources that way.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OMAP2_32KSYNCNT_REV_OFF 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OMAP2_32KSYNCNT_REV_SCHEME (0x3 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OMAP2_32KSYNCNT_CR_OFF_LOW 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OMAP2_32KSYNCNT_CR_OFF_HIGH 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct ti_32k {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) void __iomem *counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct clocksource cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static inline struct ti_32k *to_ti_32k(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return container_of(cs, struct ti_32k, cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static u64 notrace ti_32k_read_cycles(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct ti_32k *ti = to_ti_32k(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return (u64)readl_relaxed(ti->counter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static struct ti_32k ti_32k_timer = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .cs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .name = "32k_counter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .rating = 250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .read = ti_32k_read_cycles,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .mask = CLOCKSOURCE_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .flags = CLOCK_SOURCE_IS_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static u64 notrace omap_32k_read_sched_clock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return ti_32k_read_cycles(&ti_32k_timer.cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static void __init ti_32k_timer_enable_clock(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct clk *clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) clock = of_clk_get_by_name(np->parent, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (IS_ERR(clock)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Only some SoCs have a separate interface clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (PTR_ERR(clock) == -EINVAL && !strncmp("ick", name, 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) pr_warn("%s: could not get clock %s %li\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) __func__, name, PTR_ERR(clock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) error = clk_prepare_enable(clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) pr_warn("%s: could not enable %s: %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) __func__, name, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static void __init ti_32k_timer_module_init(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) void __iomem *sysc = base + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (!of_device_is_compatible(np->parent, "ti,sysc"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ti_32k_timer_enable_clock(np, "fck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ti_32k_timer_enable_clock(np, "ick");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * Force idle module as wkup domain is active with MPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * No need to tag the module disabled for ti-sysc probe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) writel_relaxed(0, sysc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int __init ti_32k_timer_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ti_32k_timer.base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (!ti_32k_timer.base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) pr_err("Can't ioremap 32k timer base\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (!of_machine_is_compatible("ti,am43"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ti_32k_timer.cs.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ti_32k_timer.counter = ti_32k_timer.base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ti_32k_timer_module_init(np, ti_32k_timer.base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * 32k sync Counter IP register offsets vary between the highlander
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * version and the legacy ones.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * The 'SCHEME' bits(30-31) of the revision register is used to identify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * the version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (readl_relaxed(ti_32k_timer.base + OMAP2_32KSYNCNT_REV_OFF) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) OMAP2_32KSYNCNT_REV_SCHEME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ti_32k_timer.counter += OMAP2_32KSYNCNT_CR_OFF_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ti_32k_timer.counter += OMAP2_32KSYNCNT_CR_OFF_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ret = clocksource_register_hz(&ti_32k_timer.cs, 32768);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) pr_err("32k_counter: can't register clocksource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) sched_clock_register(omap_32k_read_sched_clock, 32, 32768);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) TIMER_OF_DECLARE(ti_32k_timer, "ti,omap-counter32k",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ti_32k_timer_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags