Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2010 Google, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *	Colin Cross <ccross@google.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define pr_fmt(fmt)	"tegra-timer: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/cpumask.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/percpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include "timer-of.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define RTC_SECONDS		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define RTC_SHADOW_SECONDS	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define RTC_MILLISECONDS	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define TIMERUS_CNTR_1US	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define TIMERUS_USEC_CFG	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define TIMERUS_CNTR_FREEZE	0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define TIMER_PTV		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define TIMER_PTV_EN		BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define TIMER_PTV_PER		BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define TIMER_PCR		0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define TIMER_PCR_INTR_CLR	BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define TIMER1_BASE		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define TIMER2_BASE		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define TIMER3_BASE		0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define TIMER4_BASE		0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define TIMER10_BASE		0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define TIMER1_IRQ_IDX		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define TIMER10_IRQ_IDX		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define TIMER_1MHz		1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static u32 usec_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static void __iomem *timer_reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static int tegra_timer_set_next_event(unsigned long cycles,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 				      struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	 * Tegra's timer uses n+1 scheme for the counter, i.e. timer will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	 * fire after one tick if 0 is loaded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	 * The minimum and maximum numbers of oneshot ticks are defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	 * by clockevents_config_and_register(1, 0x1fffffff + 1) invocation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	 * below in the code. Hence the cycles (ticks) can't be outside of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	 * a range supportable by hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	writel_relaxed(TIMER_PTV_EN | (cycles - 1), reg_base + TIMER_PTV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static int tegra_timer_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	writel_relaxed(0, reg_base + TIMER_PTV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) static int tegra_timer_set_periodic(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	unsigned long period = timer_of_period(to_timer_of(evt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	writel_relaxed(TIMER_PTV_EN | TIMER_PTV_PER | (period - 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		       reg_base + TIMER_PTV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static irqreturn_t tegra_timer_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	struct clock_event_device *evt = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	writel_relaxed(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	evt->event_handler(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static void tegra_timer_suspend(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	writel_relaxed(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static void tegra_timer_resume(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	writel_relaxed(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static DEFINE_PER_CPU(struct timer_of, tegra_to) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	.flags = TIMER_OF_CLOCK | TIMER_OF_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	.clkevt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		.name = "tegra_timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		.set_next_event = tegra_timer_set_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		.set_state_shutdown = tegra_timer_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		.set_state_periodic = tegra_timer_set_periodic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		.set_state_oneshot = tegra_timer_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		.tick_resume = tegra_timer_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		.suspend = tegra_timer_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		.resume = tegra_timer_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int tegra_timer_setup(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	writel_relaxed(0, timer_of_base(to) + TIMER_PTV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	writel_relaxed(TIMER_PCR_INTR_CLR, timer_of_base(to) + TIMER_PCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	irq_force_affinity(to->clkevt.irq, cpumask_of(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	enable_irq(to->clkevt.irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	 * Tegra's timer uses n+1 scheme for the counter, i.e. timer will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	 * fire after one tick if 0 is loaded and thus minimum number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	 * ticks is 1. In result both of the clocksource's tick limits are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	 * higher than a minimum and maximum that hardware register can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	 * take by 1, this is then taken into account by set_next_event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	 * callback.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	clockevents_config_and_register(&to->clkevt, timer_of_rate(to),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 					1, /* min */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 					0x1fffffff + 1); /* max 29 bits + 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int tegra_timer_stop(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	to->clkevt.set_state_shutdown(&to->clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	disable_irq_nosync(to->clkevt.irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static u64 notrace tegra_read_sched_clock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	return readl_relaxed(timer_reg_base + TIMERUS_CNTR_1US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #ifdef CONFIG_ARM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static unsigned long tegra_delay_timer_read_counter_long(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	return readl_relaxed(timer_reg_base + TIMERUS_CNTR_1US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static struct delay_timer tegra_delay_timer = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	.read_current_timer = tegra_delay_timer_read_counter_long,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	.freq = TIMER_1MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static struct timer_of suspend_rtc_to = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	.flags = TIMER_OF_BASE | TIMER_OF_CLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)  * tegra_rtc_read - Reads the Tegra RTC registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)  * Care must be taken that this function is not called while the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)  * tegra_rtc driver could be executing to avoid race conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)  * on the RTC shadow register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static u64 tegra_rtc_read_ms(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	void __iomem *reg_base = timer_of_base(&suspend_rtc_to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	u32 ms = readl_relaxed(reg_base + RTC_MILLISECONDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	u32 s = readl_relaxed(reg_base + RTC_SHADOW_SECONDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	return (u64)s * MSEC_PER_SEC + ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static struct clocksource suspend_rtc_clocksource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	.name	= "tegra_suspend_timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	.rating	= 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	.read	= tegra_rtc_read_ms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	.mask	= CLOCKSOURCE_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	.flags	= CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static inline unsigned int tegra_base_for_cpu(int cpu, bool tegra20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	if (tegra20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		switch (cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			return TIMER1_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			return TIMER2_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 			return TIMER3_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			return TIMER4_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	return TIMER10_BASE + cpu * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static inline unsigned int tegra_irq_idx_for_cpu(int cpu, bool tegra20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	if (tegra20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		return TIMER1_IRQ_IDX + cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	return TIMER10_IRQ_IDX + cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static inline unsigned long tegra_rate_for_timer(struct timer_of *to,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 						 bool tegra20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	 * TIMER1-9 are fixed to 1MHz, TIMER10-13 are running off the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	 * parent clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (tegra20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		return TIMER_1MHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	return timer_of_rate(to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static int __init tegra_init_timer(struct device_node *np, bool tegra20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 				   int rating)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	struct timer_of *to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	int cpu, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	to = this_cpu_ptr(&tegra_to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	ret = timer_of_init(np, to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	timer_reg_base = timer_of_base(to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	 * Configure microsecond timers to have 1MHz clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	 * Config register is 0xqqww, where qq is "dividend", ww is "divisor"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	 * Uses n+1 scheme
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	switch (timer_of_rate(to)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	case 12000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		usec_config = 0x000b; /* (11+1)/(0+1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	case 12800000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		usec_config = 0x043f; /* (63+1)/(4+1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	case 13000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		usec_config = 0x000c; /* (12+1)/(0+1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	case 16800000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		usec_config = 0x0453; /* (83+1)/(4+1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	case 19200000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		usec_config = 0x045f; /* (95+1)/(4+1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	case 26000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		usec_config = 0x0019; /* (25+1)/(0+1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	case 38400000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		usec_config = 0x04bf; /* (191+1)/(4+1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	case 48000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		usec_config = 0x002f; /* (47+1)/(0+1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	writel_relaxed(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	for_each_possible_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		struct timer_of *cpu_to = per_cpu_ptr(&tegra_to, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		unsigned long flags = IRQF_TIMER | IRQF_NOBALANCING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		unsigned long rate = tegra_rate_for_timer(to, tegra20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		unsigned int base = tegra_base_for_cpu(cpu, tegra20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		unsigned int idx = tegra_irq_idx_for_cpu(cpu, tegra20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		unsigned int irq = irq_of_parse_and_map(np, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		if (!irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 			pr_err("failed to map irq for cpu%d\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 			ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 			goto out_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		cpu_to->clkevt.irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		cpu_to->clkevt.rating = rating;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		cpu_to->clkevt.cpumask = cpumask_of(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		cpu_to->of_base.base = timer_reg_base + base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		cpu_to->of_clk.period = rate / HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		cpu_to->of_clk.rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		ret = request_irq(cpu_to->clkevt.irq, tegra_timer_isr, flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 				  cpu_to->clkevt.name, &cpu_to->clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 			pr_err("failed to set up irq for cpu%d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 			       cpu, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 			irq_dispose_mapping(cpu_to->clkevt.irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 			cpu_to->clkevt.irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 			goto out_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	sched_clock_register(tegra_read_sched_clock, 32, TIMER_1MHz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 				    "timer_us", TIMER_1MHz, 300, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 				    clocksource_mmio_readl_up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		pr_err("failed to register clocksource: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #ifdef CONFIG_ARM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	register_current_timer_delay(&tegra_delay_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	ret = cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 				"AP_TEGRA_TIMER_STARTING", tegra_timer_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 				tegra_timer_stop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		pr_err("failed to set up cpu hp state: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) out_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	for_each_possible_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		struct timer_of *cpu_to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		cpu_to = per_cpu_ptr(&tegra_to, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		if (cpu_to->clkevt.irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 			free_irq(cpu_to->clkevt.irq, &cpu_to->clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 			irq_dispose_mapping(cpu_to->clkevt.irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	to->of_base.base = timer_reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	timer_of_cleanup(to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static int __init tegra210_init_timer(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	 * Arch-timer can't survive across power cycle of CPU core and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	 * after CPUPORESET signal due to a system design shortcoming,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	 * hence tegra-timer is more preferable on Tegra210.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	return tegra_init_timer(np, false, 460);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra210_init_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static int __init tegra20_init_timer(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	int rating;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	 * Tegra20 and Tegra30 have Cortex A9 CPU that has a TWD timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	 * that timer runs off the CPU clock and hence is subjected to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	 * a jitter caused by DVFS clock rate changes. Tegra-timer is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	 * more preferable for older Tegra's, while later SoC generations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	 * have arch-timer as a main per-CPU timer and it is not affected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	 * by DVFS changes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	if (of_machine_is_compatible("nvidia,tegra20") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	    of_machine_is_compatible("nvidia,tegra30"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		rating = 460;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		rating = 330;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	return tegra_init_timer(np, true, rating);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static int __init tegra20_init_rtc(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	ret = timer_of_init(np, &suspend_rtc_to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	return clocksource_register_hz(&suspend_rtc_clocksource, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);