Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Allwinner SoCs hstimer driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2013 Maxime Ripard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Maxime Ripard <maxime.ripard@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * License version 2.  This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/irqreturn.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define TIMER_IRQ_EN_REG		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define TIMER_IRQ_EN(val)			BIT(val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define TIMER_IRQ_ST_REG		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define TIMER_CTL_REG(val)		(0x20 * (val) + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define TIMER_CTL_ENABLE			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define TIMER_CTL_RELOAD			BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define TIMER_CTL_CLK_PRES(val)			(((val) & 0x7) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define TIMER_CTL_ONESHOT			BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define TIMER_INTVAL_LO_REG(val)	(0x20 * (val) + 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define TIMER_INTVAL_HI_REG(val)	(0x20 * (val) + 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define TIMER_CNTVAL_LO_REG(val)	(0x20 * (val) + 0x1c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define TIMER_CNTVAL_HI_REG(val)	(0x20 * (val) + 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define TIMER_SYNC_TICKS	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) struct sun5i_timer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	void __iomem		*base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	struct clk		*clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	struct notifier_block	clk_rate_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	u32			ticks_per_jiffy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define to_sun5i_timer(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	container_of(x, struct sun5i_timer, clk_rate_cb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) struct sun5i_timer_clksrc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	struct sun5i_timer	timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	struct clocksource	clksrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define to_sun5i_timer_clksrc(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	container_of(x, struct sun5i_timer_clksrc, clksrc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) struct sun5i_timer_clkevt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	struct sun5i_timer		timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	struct clock_event_device	clkevt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define to_sun5i_timer_clkevt(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	container_of(x, struct sun5i_timer_clkevt, clkevt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  * When we disable a timer, we need to wait at least for 2 cycles of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  * the timer source clock. We will use for that the clocksource timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  * that is already setup and runs at the same frequency than the other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  * timers, and we never will be disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static void sun5i_clkevt_sync(struct sun5i_timer_clkevt *ce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	u32 old = readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	while ((old - readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static void sun5i_clkevt_time_stop(struct sun5i_timer_clkevt *ce, u8 timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	writel(val & ~TIMER_CTL_ENABLE, ce->timer.base + TIMER_CTL_REG(timer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	sun5i_clkevt_sync(ce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static void sun5i_clkevt_time_setup(struct sun5i_timer_clkevt *ce, u8 timer, u32 delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	writel(delay, ce->timer.base + TIMER_INTVAL_LO_REG(timer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) static void sun5i_clkevt_time_start(struct sun5i_timer_clkevt *ce, u8 timer, bool periodic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	if (periodic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		val &= ~TIMER_CTL_ONESHOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		val |= TIMER_CTL_ONESHOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	       ce->timer.base + TIMER_CTL_REG(timer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int sun5i_clkevt_shutdown(struct clock_event_device *clkevt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	sun5i_clkevt_time_stop(ce, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int sun5i_clkevt_set_oneshot(struct clock_event_device *clkevt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	sun5i_clkevt_time_stop(ce, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	sun5i_clkevt_time_start(ce, 0, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static int sun5i_clkevt_set_periodic(struct clock_event_device *clkevt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	sun5i_clkevt_time_stop(ce, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	sun5i_clkevt_time_setup(ce, 0, ce->timer.ticks_per_jiffy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	sun5i_clkevt_time_start(ce, 0, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int sun5i_clkevt_next_event(unsigned long evt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 				   struct clock_event_device *clkevt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	sun5i_clkevt_time_stop(ce, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	sun5i_clkevt_time_setup(ce, 0, evt - TIMER_SYNC_TICKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	sun5i_clkevt_time_start(ce, 0, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static irqreturn_t sun5i_timer_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	struct sun5i_timer_clkevt *ce = (struct sun5i_timer_clkevt *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	writel(0x1, ce->timer.base + TIMER_IRQ_ST_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	ce->clkevt.event_handler(&ce->clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static u64 sun5i_clksrc_read(struct clocksource *clksrc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	struct sun5i_timer_clksrc *cs = to_sun5i_timer_clksrc(clksrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	return ~readl(cs->timer.base + TIMER_CNTVAL_LO_REG(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int sun5i_rate_cb_clksrc(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 				unsigned long event, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	struct clk_notifier_data *ndata = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	struct sun5i_timer *timer = to_sun5i_timer(nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	struct sun5i_timer_clksrc *cs = container_of(timer, struct sun5i_timer_clksrc, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	switch (event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	case PRE_RATE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		clocksource_unregister(&cs->clksrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	case POST_RATE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		clocksource_register_hz(&cs->clksrc, ndata->new_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int __init sun5i_setup_clocksource(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 					  void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 					  struct clk *clk, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	struct sun5i_timer_clksrc *cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	cs = kzalloc(sizeof(*cs), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	if (!cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		pr_err("Couldn't enable parent clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	if (!rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		pr_err("Couldn't get parent clock rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	cs->timer.base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	cs->timer.clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	cs->timer.clk_rate_cb.notifier_call = sun5i_rate_cb_clksrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	cs->timer.clk_rate_cb.next = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	ret = clk_notifier_register(clk, &cs->timer.clk_rate_cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		pr_err("Unable to register clock notifier.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	writel(~0, base + TIMER_INTVAL_LO_REG(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	       base + TIMER_CTL_REG(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	cs->clksrc.name = node->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	cs->clksrc.rating = 340;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	cs->clksrc.read = sun5i_clksrc_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	cs->clksrc.mask = CLOCKSOURCE_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	ret = clocksource_register_hz(&cs->clksrc, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		pr_err("Couldn't register clock source.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		goto err_remove_notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) err_remove_notifier:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	clk_notifier_unregister(clk, &cs->timer.clk_rate_cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) err_disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) err_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	kfree(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int sun5i_rate_cb_clkevt(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 				unsigned long event, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	struct clk_notifier_data *ndata = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	struct sun5i_timer *timer = to_sun5i_timer(nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	struct sun5i_timer_clkevt *ce = container_of(timer, struct sun5i_timer_clkevt, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	if (event == POST_RATE_CHANGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		clockevents_update_freq(&ce->clkevt, ndata->new_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		ce->timer.ticks_per_jiffy = DIV_ROUND_UP(ndata->new_rate, HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static int __init sun5i_setup_clockevent(struct device_node *node, void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 					 struct clk *clk, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	struct sun5i_timer_clkevt *ce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	ce = kzalloc(sizeof(*ce), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	if (!ce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		pr_err("Couldn't enable parent clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	if (!rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		pr_err("Couldn't get parent clock rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	ce->timer.base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	ce->timer.ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	ce->timer.clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	ce->timer.clk_rate_cb.notifier_call = sun5i_rate_cb_clkevt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	ce->timer.clk_rate_cb.next = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	ret = clk_notifier_register(clk, &ce->timer.clk_rate_cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		pr_err("Unable to register clock notifier.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	ce->clkevt.name = node->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	ce->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	ce->clkevt.set_next_event = sun5i_clkevt_next_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	ce->clkevt.set_state_shutdown = sun5i_clkevt_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	ce->clkevt.set_state_periodic = sun5i_clkevt_set_periodic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	ce->clkevt.set_state_oneshot = sun5i_clkevt_set_oneshot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	ce->clkevt.tick_resume = sun5i_clkevt_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	ce->clkevt.rating = 340;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	ce->clkevt.irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	ce->clkevt.cpumask = cpu_possible_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	/* Enable timer0 interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	val = readl(base + TIMER_IRQ_EN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	writel(val | TIMER_IRQ_EN(0), base + TIMER_IRQ_EN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	clockevents_config_and_register(&ce->clkevt, rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 					TIMER_SYNC_TICKS, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	ret = request_irq(irq, sun5i_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 			  "sun5i_timer0", ce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		pr_err("Unable to register interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		goto err_remove_notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) err_remove_notifier:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	clk_notifier_unregister(clk, &ce->timer.clk_rate_cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) err_disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) err_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	kfree(ce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static int __init sun5i_timer_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	struct reset_control *rstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	void __iomem *timer_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	timer_base = of_io_request_and_map(node, 0, of_node_full_name(node));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	if (IS_ERR(timer_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		pr_err("Can't map registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		return PTR_ERR(timer_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	irq = irq_of_parse_and_map(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	if (irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		pr_err("Can't parse IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	clk = of_clk_get(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		pr_err("Can't get timer clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	rstc = of_reset_control_get(node, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	if (!IS_ERR(rstc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		reset_control_deassert(rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	ret = sun5i_setup_clocksource(node, timer_base, clk, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	return sun5i_setup_clockevent(node, timer_base, clk, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) TIMER_OF_DECLARE(sun5i_a13, "allwinner,sun5i-a13-hstimer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 			   sun5i_timer_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) TIMER_OF_DECLARE(sun7i_a20, "allwinner,sun7i-a20-hstimer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 			   sun5i_timer_init);