Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Allwinner A1X SoCs timer handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2012 Maxime Ripard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Maxime Ripard <maxime.ripard@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Based on code from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Benn Huang <benn@allwinnertech.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * License version 2.  This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/irqreturn.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include "timer-of.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define TIMER_IRQ_EN_REG	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define TIMER_IRQ_EN(val)		BIT(val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define TIMER_IRQ_ST_REG	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define TIMER_CTL_REG(val)	(0x10 * val + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define TIMER_CTL_ENABLE		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define TIMER_CTL_RELOAD		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define TIMER_CTL_CLK_SRC(val)		(((val) & 0x3) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define TIMER_CTL_CLK_SRC_OSC24M		(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define TIMER_CTL_CLK_PRES(val)		(((val) & 0x7) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define TIMER_CTL_ONESHOT		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define TIMER_INTVAL_REG(val)	(0x10 * (val) + 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define TIMER_CNTVAL_REG(val)	(0x10 * (val) + 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define TIMER_SYNC_TICKS	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  * When we disable a timer, we need to wait at least for 2 cycles of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  * the timer source clock. We will use for that the clocksource timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  * that is already setup and runs at the same frequency than the other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  * timers, and we never will be disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static void sun4i_clkevt_sync(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	u32 old = readl(base + TIMER_CNTVAL_REG(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	while ((old - readl(base + TIMER_CNTVAL_REG(1))) < TIMER_SYNC_TICKS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static void sun4i_clkevt_time_stop(void __iomem *base, u8 timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	u32 val = readl(base + TIMER_CTL_REG(timer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	writel(val & ~TIMER_CTL_ENABLE, base + TIMER_CTL_REG(timer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	sun4i_clkevt_sync(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) static void sun4i_clkevt_time_setup(void __iomem *base, u8 timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 				    unsigned long delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	writel(delay, base + TIMER_INTVAL_REG(timer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) static void sun4i_clkevt_time_start(void __iomem *base, u8 timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 				    bool periodic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	u32 val = readl(base + TIMER_CTL_REG(timer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	if (periodic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		val &= ~TIMER_CTL_ONESHOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		val |= TIMER_CTL_ONESHOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	       base + TIMER_CTL_REG(timer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) static int sun4i_clkevt_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	struct timer_of *to = to_timer_of(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	sun4i_clkevt_time_stop(timer_of_base(to), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) static int sun4i_clkevt_set_oneshot(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	struct timer_of *to = to_timer_of(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	sun4i_clkevt_time_stop(timer_of_base(to), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	sun4i_clkevt_time_start(timer_of_base(to), 0, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int sun4i_clkevt_set_periodic(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	struct timer_of *to = to_timer_of(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	sun4i_clkevt_time_stop(timer_of_base(to), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	sun4i_clkevt_time_setup(timer_of_base(to), 0, timer_of_period(to));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	sun4i_clkevt_time_start(timer_of_base(to), 0, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int sun4i_clkevt_next_event(unsigned long evt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 				   struct clock_event_device *clkevt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	struct timer_of *to = to_timer_of(clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	sun4i_clkevt_time_stop(timer_of_base(to), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	sun4i_clkevt_time_setup(timer_of_base(to), 0, evt - TIMER_SYNC_TICKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	sun4i_clkevt_time_start(timer_of_base(to), 0, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void sun4i_timer_clear_interrupt(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	writel(TIMER_IRQ_EN(0), base + TIMER_IRQ_ST_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	struct timer_of *to = to_timer_of(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	sun4i_timer_clear_interrupt(timer_of_base(to));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	evt->event_handler(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static struct timer_of to = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	.flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	.clkevt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		.name = "sun4i_tick",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		.rating = 350,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		.set_state_shutdown = sun4i_clkevt_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		.set_state_periodic = sun4i_clkevt_set_periodic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		.set_state_oneshot = sun4i_clkevt_set_oneshot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		.tick_resume = sun4i_clkevt_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		.set_next_event = sun4i_clkevt_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		.cpumask = cpu_possible_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	.of_irq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		.handler = sun4i_timer_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		.flags = IRQF_TIMER | IRQF_IRQPOLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static u64 notrace sun4i_timer_sched_read(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	return ~readl(timer_of_base(&to) + TIMER_CNTVAL_REG(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int __init sun4i_timer_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	ret = timer_of_init(node, &to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	writel(~0, timer_of_base(&to) + TIMER_INTVAL_REG(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	       TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	       timer_of_base(&to) + TIMER_CTL_REG(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	 * sched_clock_register does not have priorities, and on sun6i and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	 * later there is a better sched_clock registered by arm_arch_timer.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	if (of_machine_is_compatible("allwinner,sun4i-a10") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	    of_machine_is_compatible("allwinner,sun5i-a13") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	    of_machine_is_compatible("allwinner,sun5i-a10s") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	    of_machine_is_compatible("allwinner,suniv-f1c100s"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		sched_clock_register(sun4i_timer_sched_read, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 				     timer_of_rate(&to));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	ret = clocksource_mmio_init(timer_of_base(&to) + TIMER_CNTVAL_REG(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 				    node->name, timer_of_rate(&to), 350, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 				    clocksource_mmio_readl_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		pr_err("Failed to register clocksource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	       timer_of_base(&to) + TIMER_CTL_REG(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	/* Make sure timer is stopped before playing with interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	sun4i_clkevt_time_stop(timer_of_base(&to), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	/* clear timer0 interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	sun4i_timer_clear_interrupt(timer_of_base(&to));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 					TIMER_SYNC_TICKS, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	/* Enable timer0 interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	val = readl(timer_of_base(&to) + TIMER_IRQ_EN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	writel(val | TIMER_IRQ_EN(0), timer_of_base(&to) + TIMER_IRQ_EN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) TIMER_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		       sun4i_timer_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) TIMER_OF_DECLARE(sun8i_a23, "allwinner,sun8i-a23-timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		 sun4i_timer_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) TIMER_OF_DECLARE(sun8i_v3s, "allwinner,sun8i-v3s-timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		 sun4i_timer_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) TIMER_OF_DECLARE(suniv, "allwinner,suniv-f1c100s-timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		       sun4i_timer_init);