^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) Maxime Coquelin 2015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Inspired by time-efm32.c from Uwe Kleine-Koenig
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "timer-of.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TIM_CR1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TIM_DIER 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TIM_SR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TIM_EGR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TIM_CNT 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TIM_PSC 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TIM_ARR 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TIM_CCR1 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TIM_CR1_CEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TIM_CR1_UDIS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TIM_CR1_OPM BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TIM_CR1_ARPE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TIM_DIER_UIE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TIM_DIER_CC1IE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TIM_SR_UIF BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TIM_EGR_UG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TIM_PSC_MAX USHRT_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TIM_PSC_CLKRATE 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct stm32_timer_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) int bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * stm32_timer_of_bits_set - set accessor helper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * @to: a timer_of structure pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @bits: the number of bits (16 or 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * Accessor helper to set the number of bits in the timer-of private
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static void stm32_timer_of_bits_set(struct timer_of *to, int bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct stm32_timer_private *pd = to->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) pd->bits = bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * stm32_timer_of_bits_get - get accessor helper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * @to: a timer_of structure pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * Accessor helper to get the number of bits in the timer-of private
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * Returns an integer corresponding to the number of bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static int stm32_timer_of_bits_get(struct timer_of *to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct stm32_timer_private *pd = to->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return pd->bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static void __iomem *stm32_timer_cnt __read_mostly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static u64 notrace stm32_read_sched_clock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return readl_relaxed(stm32_timer_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static struct delay_timer stm32_timer_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static unsigned long stm32_read_delay(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return readl_relaxed(stm32_timer_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static void stm32_clock_event_disable(struct timer_of *to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) writel_relaxed(0, timer_of_base(to) + TIM_DIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * stm32_timer_start - Start the counter without event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * @to: a timer_of structure pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * Start the timer in order to have the counter reset and start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * incrementing but disable interrupt event when there is a counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * overflow. By default, the counter direction is used as upcounter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static void stm32_timer_start(struct timer_of *to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) writel_relaxed(TIM_CR1_UDIS | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int stm32_clock_event_shutdown(struct clock_event_device *clkevt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct timer_of *to = to_timer_of(clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) stm32_clock_event_disable(to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int stm32_clock_event_set_next_event(unsigned long evt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct clock_event_device *clkevt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct timer_of *to = to_timer_of(clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned long now, next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) next = readl_relaxed(timer_of_base(to) + TIM_CNT) + evt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) writel_relaxed(next, timer_of_base(to) + TIM_CCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) now = readl_relaxed(timer_of_base(to) + TIM_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if ((next - now) > evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) writel_relaxed(TIM_DIER_CC1IE, timer_of_base(to) + TIM_DIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int stm32_clock_event_set_periodic(struct clock_event_device *clkevt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct timer_of *to = to_timer_of(clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) stm32_timer_start(to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return stm32_clock_event_set_next_event(timer_of_period(to), clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int stm32_clock_event_set_oneshot(struct clock_event_device *clkevt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct timer_of *to = to_timer_of(clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) stm32_timer_start(to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct clock_event_device *clkevt = (struct clock_event_device *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct timer_of *to = to_timer_of(clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) writel_relaxed(0, timer_of_base(to) + TIM_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (clockevent_state_periodic(clkevt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) stm32_clock_event_set_periodic(clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) stm32_clock_event_shutdown(clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) clkevt->event_handler(clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * stm32_timer_width - Sort out the timer width (32/16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * @to: a pointer to a timer-of structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * Write the 32-bit max value and read/return the result. If the timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * is 32 bits wide, the result will be UINT_MAX, otherwise it will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * be truncated by the 16-bit register to USHRT_MAX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static void __init stm32_timer_set_width(struct timer_of *to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) writel_relaxed(UINT_MAX, timer_of_base(to) + TIM_ARR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) width = readl_relaxed(timer_of_base(to) + TIM_ARR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) stm32_timer_of_bits_set(to, width == UINT_MAX ? 32 : 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * stm32_timer_set_prescaler - Compute and set the prescaler register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * @to: a pointer to a timer-of structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * Depending on the timer width, compute the prescaler to always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * target a 10MHz timer rate for 16 bits. 32-bit timers are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * considered precise and long enough to not use the prescaler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static void __init stm32_timer_set_prescaler(struct timer_of *to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int prescaler = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (stm32_timer_of_bits_get(to) != 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) prescaler = DIV_ROUND_CLOSEST(timer_of_rate(to),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) TIM_PSC_CLKRATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * The prescaler register is an u16, the variable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * can't be greater than TIM_PSC_MAX, let's cap it in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * this case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) prescaler = prescaler < TIM_PSC_MAX ? prescaler : TIM_PSC_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) writel_relaxed(0, timer_of_base(to) + TIM_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* Adjust rate and period given the prescaler value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) to->of_clk.rate = DIV_ROUND_CLOSEST(to->of_clk.rate, prescaler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) to->of_clk.period = DIV_ROUND_UP(to->of_clk.rate, HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static int __init stm32_clocksource_init(struct timer_of *to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u32 bits = stm32_timer_of_bits_get(to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) const char *name = to->np->full_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * This driver allows to register several timers and relies on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * the generic time framework to select the right one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * However, nothing allows to do the same for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * sched_clock. We are not interested in a sched_clock for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * 16-bit timers but only for the 32-bit one, so if no 32-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * timer is registered yet, we select this 32-bit timer as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * sched_clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (bits == 32 && !stm32_timer_cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * Start immediately the counter as we will be using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * it right after.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) stm32_timer_start(to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) stm32_timer_cnt = timer_of_base(to) + TIM_CNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) sched_clock_register(stm32_read_sched_clock, bits, timer_of_rate(to));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) pr_info("%s: STM32 sched_clock registered\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) stm32_timer_delay.read_current_timer = stm32_read_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) stm32_timer_delay.freq = timer_of_rate(to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) register_current_timer_delay(&stm32_timer_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) pr_info("%s: STM32 delay timer registered\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return clocksource_mmio_init(timer_of_base(to) + TIM_CNT, name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) timer_of_rate(to), bits == 32 ? 250 : 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) bits, clocksource_mmio_readl_up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static void __init stm32_clockevent_init(struct timer_of *to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u32 bits = stm32_timer_of_bits_get(to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) to->clkevt.name = to->np->full_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) to->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) to->clkevt.set_state_shutdown = stm32_clock_event_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) to->clkevt.set_state_periodic = stm32_clock_event_set_periodic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) to->clkevt.set_state_oneshot = stm32_clock_event_set_oneshot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) to->clkevt.tick_resume = stm32_clock_event_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) to->clkevt.set_next_event = stm32_clock_event_set_next_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) to->clkevt.rating = bits == 32 ? 250 : 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) clockevents_config_and_register(&to->clkevt, timer_of_rate(to), 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) (1 << bits) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) to->np, bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static int __init stm32_timer_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct reset_control *rstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct timer_of *to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) to = kzalloc(sizeof(*to), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (!to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) to->flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) to->of_irq.handler = stm32_clock_event_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ret = timer_of_init(node, to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) to->private_data = kzalloc(sizeof(struct stm32_timer_private),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (!to->private_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) goto deinit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) rstc = of_reset_control_get(node, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (!IS_ERR(rstc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) reset_control_assert(rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) reset_control_deassert(rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) stm32_timer_set_width(to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) stm32_timer_set_prescaler(to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ret = stm32_clocksource_init(to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) goto deinit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) stm32_clockevent_init(to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) deinit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) timer_of_cleanup(to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) kfree(to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) TIMER_OF_DECLARE(stm32, "st,stm32-timer", stm32_timer_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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