^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Authors: Benjamin Gaignard <benjamin.gaignard@st.com> for STMicroelectronics.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Pascal Paillet <p.paillet@st.com> for STMicroelectronics.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mfd/stm32-lptimer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm_wakeirq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CFGR_PSC_OFFSET 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define STM32_LP_RATING 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define STM32_TARGET_CLKRATE (32000 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define STM32_LP_MAX_PSC 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct stm32_lp_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct regmap *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct clock_event_device clkevt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) unsigned long period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static struct stm32_lp_private*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) to_priv(struct clock_event_device *clkevt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) return container_of(clkevt, struct stm32_lp_private, clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static int stm32_clkevent_lp_shutdown(struct clock_event_device *clkevt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct stm32_lp_private *priv = to_priv(clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) regmap_write(priv->reg, STM32_LPTIM_CR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) regmap_write(priv->reg, STM32_LPTIM_IER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* clear pending flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) regmap_write(priv->reg, STM32_LPTIM_ICR, STM32_LPTIM_ARRMCF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static int stm32_clkevent_lp_set_timer(unsigned long evt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct clock_event_device *clkevt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) int is_periodic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct stm32_lp_private *priv = to_priv(clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* disable LPTIMER to be able to write into IER register*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) regmap_write(priv->reg, STM32_LPTIM_CR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* enable ARR interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) regmap_write(priv->reg, STM32_LPTIM_IER, STM32_LPTIM_ARRMIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* enable LPTIMER to be able to write into ARR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) regmap_write(priv->reg, STM32_LPTIM_CR, STM32_LPTIM_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* set next event counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) regmap_write(priv->reg, STM32_LPTIM_ARR, evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* start counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (is_periodic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) regmap_write(priv->reg, STM32_LPTIM_CR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) STM32_LPTIM_CNTSTRT | STM32_LPTIM_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) regmap_write(priv->reg, STM32_LPTIM_CR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) STM32_LPTIM_SNGSTRT | STM32_LPTIM_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int stm32_clkevent_lp_set_next_event(unsigned long evt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct clock_event_device *clkevt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return stm32_clkevent_lp_set_timer(evt, clkevt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) clockevent_state_periodic(clkevt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static int stm32_clkevent_lp_set_periodic(struct clock_event_device *clkevt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct stm32_lp_private *priv = to_priv(clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return stm32_clkevent_lp_set_timer(priv->period, clkevt, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static int stm32_clkevent_lp_set_oneshot(struct clock_event_device *clkevt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct stm32_lp_private *priv = to_priv(clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return stm32_clkevent_lp_set_timer(priv->period, clkevt, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static irqreturn_t stm32_clkevent_lp_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct clock_event_device *clkevt = (struct clock_event_device *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct stm32_lp_private *priv = to_priv(clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) regmap_write(priv->reg, STM32_LPTIM_ICR, STM32_LPTIM_ARRMCF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (clkevt->event_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) clkevt->event_handler(clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void stm32_clkevent_lp_set_prescaler(struct stm32_lp_private *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned long *rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) for (i = 0; i <= STM32_LP_MAX_PSC; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (DIV_ROUND_CLOSEST(*rate, 1 << i) < STM32_TARGET_CLKRATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) regmap_write(priv->reg, STM32_LPTIM_CFGR, i << CFGR_PSC_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Adjust rate and period given the prescaler value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) *rate = DIV_ROUND_CLOSEST(*rate, (1 << i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) priv->period = DIV_ROUND_UP(*rate, HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static void stm32_clkevent_lp_init(struct stm32_lp_private *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct device_node *np, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) priv->clkevt.name = np->full_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) priv->clkevt.cpumask = cpu_possible_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) priv->clkevt.features = CLOCK_EVT_FEAT_PERIODIC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) CLOCK_EVT_FEAT_ONESHOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) priv->clkevt.set_state_shutdown = stm32_clkevent_lp_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) priv->clkevt.set_state_periodic = stm32_clkevent_lp_set_periodic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) priv->clkevt.set_state_oneshot = stm32_clkevent_lp_set_oneshot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) priv->clkevt.set_next_event = stm32_clkevent_lp_set_next_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) priv->clkevt.rating = STM32_LP_RATING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) clockevents_config_and_register(&priv->clkevt, rate, 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) STM32_LPTIM_MAX_ARR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int stm32_clkevent_lp_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct stm32_lptimer *ddata = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct stm32_lp_private *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) priv->reg = ddata->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ret = clk_prepare_enable(ddata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) rate = clk_get_rate(ddata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (!rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) goto out_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) irq = platform_get_irq(to_platform_device(pdev->dev.parent), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ret = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) goto out_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (of_property_read_bool(pdev->dev.parent->of_node, "wakeup-source")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ret = device_init_wakeup(&pdev->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) goto out_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ret = dev_pm_set_wake_irq(&pdev->dev, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) goto out_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ret = devm_request_irq(&pdev->dev, irq, stm32_clkevent_lp_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) IRQF_TIMER, pdev->name, &priv->clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) goto out_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) stm32_clkevent_lp_set_prescaler(priv, &rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) stm32_clkevent_lp_init(priv, pdev->dev.parent->of_node, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) priv->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) out_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) clk_disable_unprepare(ddata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static int stm32_clkevent_lp_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return -EBUSY; /* cannot unregister clockevent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static const struct of_device_id stm32_clkevent_lp_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { .compatible = "st,stm32-lptimer-timer", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) MODULE_DEVICE_TABLE(of, stm32_clkevent_lp_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static struct platform_driver stm32_clkevent_lp_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .probe = stm32_clkevent_lp_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .remove = stm32_clkevent_lp_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .name = "stm32-lptimer-timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .of_match_table = of_match_ptr(stm32_clkevent_lp_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) module_platform_driver(stm32_clkevent_lp_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) MODULE_ALIAS("platform:stm32-lptimer-timer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) MODULE_DESCRIPTION("STMicroelectronics STM32 clockevent low power driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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