Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2017 Spreadtrum Communications Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include "timer-of.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define TIMER_NAME		"sprd_timer"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define TIMER_LOAD_LO		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define TIMER_LOAD_HI		0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define TIMER_VALUE_LO		0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define TIMER_VALUE_HI		0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define TIMER_CTL		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define TIMER_CTL_PERIOD_MODE	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define TIMER_CTL_ENABLE	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define TIMER_CTL_64BIT_WIDTH	BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define TIMER_INT		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define TIMER_INT_EN		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define TIMER_INT_RAW_STS	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define TIMER_INT_MASK_STS	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define TIMER_INT_CLR		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define TIMER_VALUE_SHDW_LO	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define TIMER_VALUE_SHDW_HI	0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define TIMER_VALUE_LO_MASK	GENMASK(31, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) static void sprd_timer_enable(void __iomem *base, u32 flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	u32 val = readl_relaxed(base + TIMER_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	val |= TIMER_CTL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	if (flag & TIMER_CTL_64BIT_WIDTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		val |= TIMER_CTL_64BIT_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		val &= ~TIMER_CTL_64BIT_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	if (flag & TIMER_CTL_PERIOD_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		val |= TIMER_CTL_PERIOD_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		val &= ~TIMER_CTL_PERIOD_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	writel_relaxed(val, base + TIMER_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static void sprd_timer_disable(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	u32 val = readl_relaxed(base + TIMER_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	val &= ~TIMER_CTL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	writel_relaxed(val, base + TIMER_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static void sprd_timer_update_counter(void __iomem *base, unsigned long cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	writel_relaxed(cycles & TIMER_VALUE_LO_MASK, base + TIMER_LOAD_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	writel_relaxed(0, base + TIMER_LOAD_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) static void sprd_timer_enable_interrupt(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	writel_relaxed(TIMER_INT_EN, base + TIMER_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) static void sprd_timer_clear_interrupt(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	u32 val = readl_relaxed(base + TIMER_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	val |= TIMER_INT_CLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	writel_relaxed(val, base + TIMER_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static int sprd_timer_set_next_event(unsigned long cycles,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 				     struct clock_event_device *ce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	struct timer_of *to = to_timer_of(ce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	sprd_timer_disable(timer_of_base(to));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	sprd_timer_update_counter(timer_of_base(to), cycles);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	sprd_timer_enable(timer_of_base(to), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static int sprd_timer_set_periodic(struct clock_event_device *ce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	struct timer_of *to = to_timer_of(ce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	sprd_timer_disable(timer_of_base(to));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	sprd_timer_update_counter(timer_of_base(to), timer_of_period(to));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	sprd_timer_enable(timer_of_base(to), TIMER_CTL_PERIOD_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int sprd_timer_shutdown(struct clock_event_device *ce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	struct timer_of *to = to_timer_of(ce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	sprd_timer_disable(timer_of_base(to));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static irqreturn_t sprd_timer_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct clock_event_device *ce = (struct clock_event_device *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	struct timer_of *to = to_timer_of(ce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	sprd_timer_clear_interrupt(timer_of_base(to));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	if (clockevent_state_oneshot(ce))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		sprd_timer_disable(timer_of_base(to));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	ce->event_handler(ce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static struct timer_of to = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	.flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	.clkevt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		.name = TIMER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		.rating = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		.features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_PERIODIC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			CLOCK_EVT_FEAT_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		.set_state_shutdown = sprd_timer_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		.set_state_periodic = sprd_timer_set_periodic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		.set_next_event = sprd_timer_set_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		.cpumask = cpu_possible_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	.of_irq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		.handler = sprd_timer_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		.flags = IRQF_TIMER | IRQF_IRQPOLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int __init sprd_timer_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	ret = timer_of_init(np, &to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	sprd_timer_enable_interrupt(timer_of_base(&to));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 					1, UINT_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static struct timer_of suspend_to = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	.flags = TIMER_OF_BASE | TIMER_OF_CLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static u64 sprd_suspend_timer_read(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	return ~(u64)readl_relaxed(timer_of_base(&suspend_to) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 				   TIMER_VALUE_SHDW_LO) & cs->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int sprd_suspend_timer_enable(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	sprd_timer_update_counter(timer_of_base(&suspend_to),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 				  TIMER_VALUE_LO_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	sprd_timer_enable(timer_of_base(&suspend_to), TIMER_CTL_PERIOD_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static void sprd_suspend_timer_disable(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	sprd_timer_disable(timer_of_base(&suspend_to));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static struct clocksource suspend_clocksource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	.name	= "sprd_suspend_timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	.rating	= 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	.read	= sprd_suspend_timer_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	.enable = sprd_suspend_timer_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	.disable = sprd_suspend_timer_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	.mask	= CLOCKSOURCE_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	.flags	= CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static int __init sprd_suspend_timer_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	ret = timer_of_init(np, &suspend_to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	clocksource_register_hz(&suspend_clocksource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 				timer_of_rate(&suspend_to));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) TIMER_OF_DECLARE(sc9860_timer, "sprd,sc9860-timer", sprd_timer_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) TIMER_OF_DECLARE(sc9860_persistent_timer, "sprd,sc9860-suspend-timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		 sprd_suspend_timer_init);