^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/drivers/clocksource/timer-sp.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1999 - 2003 ARM Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2000 Deep Blue Solutions Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "timer-sp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* Hisilicon 64-bit timer(a variant of ARM SP804) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define HISI_TIMER_1_BASE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define HISI_TIMER_2_BASE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define HISI_TIMER_LOAD 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define HISI_TIMER_LOAD_H 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define HISI_TIMER_VALUE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define HISI_TIMER_VALUE_H 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HISI_TIMER_CTRL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HISI_TIMER_INTCLR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define HISI_TIMER_RIS 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define HISI_TIMER_MIS 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define HISI_TIMER_BGLOAD 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define HISI_TIMER_BGLOAD_H 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct sp804_timer __initdata arm_sp804_timer = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .load = TIMER_LOAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .value = TIMER_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .ctrl = TIMER_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .intclr = TIMER_INTCLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .timer_base = {TIMER_1_BASE, TIMER_2_BASE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .width = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct sp804_timer __initdata hisi_sp804_timer = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .load = HISI_TIMER_LOAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .load_h = HISI_TIMER_LOAD_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .value = HISI_TIMER_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .value_h = HISI_TIMER_VALUE_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .ctrl = HISI_TIMER_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .intclr = HISI_TIMER_INTCLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .timer_base = {HISI_TIMER_1_BASE, HISI_TIMER_2_BASE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .width = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static struct sp804_clkevt sp804_clkevt[NR_TIMERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static long __init sp804_get_clock_rate(struct clk *clk, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (!clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) clk = clk_get_sys("sp804", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) pr_err("sp804: %s clock not found: %ld\n", name, PTR_ERR(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) err = clk_prepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) pr_err("sp804: clock failed to prepare: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) err = clk_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) pr_err("sp804: clock failed to enable: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) clk_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (rate < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) pr_err("sp804: clock failed to get rate: %ld\n", rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) clk_disable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) clk_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static struct sp804_clkevt * __init sp804_clkevt_get(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) for (i = 0; i < NR_TIMERS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (sp804_clkevt[i].base == base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return &sp804_clkevt[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* It's impossible to reach here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static struct sp804_clkevt *sched_clkevt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static u64 notrace sp804_read(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return ~readl_relaxed(sched_clkevt->value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int __init sp804_clocksource_and_sched_clock_init(void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct clk *clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int use_sched_clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct sp804_clkevt *clkevt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) rate = sp804_get_clock_rate(clk, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (rate < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) clkevt = sp804_clkevt_get(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) writel(0, clkevt->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) writel(0xffffffff, clkevt->load);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) writel(0xffffffff, clkevt->value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (clkevt->width == 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) writel(0xffffffff, clkevt->load_h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) writel(0xffffffff, clkevt->value_h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) clkevt->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) clocksource_mmio_init(clkevt->value, name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) rate, 200, 32, clocksource_mmio_readl_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (use_sched_clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) sched_clkevt = clkevt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) sched_clock_register(sp804_read, 32, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static struct sp804_clkevt *common_clkevt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * IRQ handler for the timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct clock_event_device *evt = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* clear the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) writel(1, common_clkevt->intclr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) evt->event_handler(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static inline void timer_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) writel(0, common_clkevt->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int sp804_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) timer_shutdown(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int sp804_set_periodic(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) timer_shutdown(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) writel(common_clkevt->reload, common_clkevt->load);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) writel(ctrl, common_clkevt->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int sp804_set_next_event(unsigned long next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) TIMER_CTRL_ONESHOT | TIMER_CTRL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) writel(next, common_clkevt->load);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) writel(ctrl, common_clkevt->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static struct clock_event_device sp804_clockevent = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .features = CLOCK_EVT_FEAT_PERIODIC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) CLOCK_EVT_FEAT_ONESHOT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) CLOCK_EVT_FEAT_DYNIRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .set_state_shutdown = sp804_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .set_state_periodic = sp804_set_periodic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .set_state_oneshot = sp804_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .tick_resume = sp804_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .set_next_event = sp804_set_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .rating = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int __init sp804_clockevents_init(void __iomem *base, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct clk *clk, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct clock_event_device *evt = &sp804_clockevent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) rate = sp804_get_clock_rate(clk, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (rate < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) common_clkevt = sp804_clkevt_get(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) common_clkevt->reload = DIV_ROUND_CLOSEST(rate, HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) evt->name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) evt->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) evt->cpumask = cpu_possible_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) writel(0, common_clkevt->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (request_irq(irq, sp804_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) "timer", &sp804_clockevent))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) pr_err("%s: request_irq() failed\n", "timer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) clockevents_config_and_register(evt, rate, 0xf, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static void __init sp804_clkevt_init(struct sp804_timer *timer, void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) for (i = 0; i < NR_TIMERS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) void __iomem *timer_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct sp804_clkevt *clkevt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) timer_base = base + timer->timer_base[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) clkevt = &sp804_clkevt[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) clkevt->base = timer_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) clkevt->load = timer_base + timer->load;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) clkevt->load_h = timer_base + timer->load_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) clkevt->value = timer_base + timer->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) clkevt->value_h = timer_base + timer->value_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) clkevt->ctrl = timer_base + timer->ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) clkevt->intclr = timer_base + timer->intclr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) clkevt->width = timer->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static int __init sp804_of_init(struct device_node *np, struct sp804_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static bool initialized = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) void __iomem *timer1_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) void __iomem *timer2_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int irq, ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u32 irq_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct clk *clk1, *clk2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) const char *name = of_get_property(np, "compatible", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (!base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) timer1_base = base + timer->timer_base[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) timer2_base = base + timer->timer_base[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* Ensure timers are disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) writel(0, timer1_base + timer->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) writel(0, timer2_base + timer->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (initialized || !of_device_is_available(np)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) clk1 = of_clk_get(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (IS_ERR(clk1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) clk1 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* Get the 2nd clock if the timer has 3 timer clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (of_clk_get_parent_count(np) == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) clk2 = of_clk_get(np, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (IS_ERR(clk2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) pr_err("sp804: %pOFn clock not found: %d\n", np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) (int)PTR_ERR(clk2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) clk2 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) clk2 = clk1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) irq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) sp804_clkevt_init(timer, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) of_property_read_u32(np, "arm,sp804-has-irq", &irq_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (irq_num == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ret = sp804_clockevents_init(timer2_base, irq, clk2, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ret = sp804_clocksource_and_sched_clock_init(timer1_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) name, clk1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ret = sp804_clockevents_init(timer1_base, irq, clk1, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ret = sp804_clocksource_and_sched_clock_init(timer2_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) name, clk2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) initialized = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static int __init arm_sp804_of_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return sp804_of_init(np, &arm_sp804_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) TIMER_OF_DECLARE(sp804, "arm,sp804", arm_sp804_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static int __init hisi_sp804_of_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return sp804_of_init(np, &hisi_sp804_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) TIMER_OF_DECLARE(hisi_sp804, "hisilicon,sp804", hisi_sp804_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static int __init integrator_cp_of_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static int init_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) int irq, ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) const char *name = of_get_property(np, "compatible", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) pr_err("Failed to iomap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) clk = of_clk_get(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) pr_err("Failed to get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* Ensure timer is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) writel(0, base + arm_sp804_timer.ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (init_count == 2 || !of_device_is_available(np))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) sp804_clkevt_init(&arm_sp804_timer, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (!init_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ret = sp804_clocksource_and_sched_clock_init(base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) name, clk, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) irq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ret = sp804_clockevents_init(base, irq, clk, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) init_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) TIMER_OF_DECLARE(intcp, "arm,integrator-cp-timer", integrator_cp_of_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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