Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * ARM timer implementation, found in Integrator, Versatile and Realview
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * platforms.  Not all platforms support all registers and bits in these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * registers, so we mark them with A for Integrator AP, C for Integrator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * CP, V for Versatile and R for Realview.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Integrator AP has 16-bit timers, Integrator CP, Versatile and Realview
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * can have 16-bit or 32-bit selectable via a bit in the control register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * Every SP804 contains two identical timers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define NR_TIMERS	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define TIMER_1_BASE	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define TIMER_2_BASE	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TIMER_LOAD	0x00			/* ACVR rw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TIMER_VALUE	0x04			/* ACVR ro */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TIMER_CTRL	0x08			/* ACVR rw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TIMER_CTRL_ONESHOT	(1 << 0)	/*  CVR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TIMER_CTRL_32BIT	(1 << 1)	/*  CVR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TIMER_CTRL_DIV1		(0 << 2)	/* ACVR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TIMER_CTRL_DIV16	(1 << 2)	/* ACVR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TIMER_CTRL_DIV256	(2 << 2)	/* ACVR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TIMER_CTRL_IE		(1 << 5)	/*   VR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TIMER_CTRL_PERIODIC	(1 << 6)	/* ACVR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TIMER_CTRL_ENABLE	(1 << 7)	/* ACVR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TIMER_INTCLR	0x0c			/* ACVR wo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TIMER_RIS	0x10			/*  CVR ro */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TIMER_MIS	0x14			/*  CVR ro */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TIMER_BGLOAD	0x18			/*  CVR rw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct sp804_timer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	int load;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	int load_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	int value_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	int ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	int intclr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	int ris;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	int mis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	int bgload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	int bgload_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	int timer_base[NR_TIMERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	int width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct sp804_clkevt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	void __iomem *load;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	void __iomem *load_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	void __iomem *value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	void __iomem *value_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	void __iomem *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	void __iomem *intclr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	void __iomem *ris;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	void __iomem *mis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	void __iomem *bgload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	void __iomem *bgload_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	unsigned long reload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	int width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };