Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Rockchip timer support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) Daniel Lezcano <daniel.lezcano@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define TIMER_NAME "rk_timer"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define TIMER_LOAD_COUNT0	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define TIMER_LOAD_COUNT1	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define TIMER_CURRENT_VALUE0	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define TIMER_CURRENT_VALUE1	0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define TIMER_CONTROL_REG3288	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define TIMER_CONTROL_REG3399	0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define TIMER_INT_STATUS	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define TIMER_DISABLE		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define TIMER_ENABLE		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define TIMER_MODE_FREE_RUNNING			(0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define TIMER_MODE_USER_DEFINED_COUNT		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define TIMER_INT_UNMASK			(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) struct rk_timer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	void __iomem *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	u32 freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) struct rk_clkevt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	struct clock_event_device ce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	struct rk_timer timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static struct rk_clkevt *rk_clkevt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #ifndef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static struct rk_timer *rk_clksrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static inline struct rk_timer *rk_timer(struct clock_event_device *ce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	return &container_of(ce, struct rk_clkevt, ce)->timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static inline void rk_timer_disable(struct rk_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	writel_relaxed(TIMER_DISABLE, timer->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static inline void rk_timer_enable(struct rk_timer *timer, u32 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	writel_relaxed(TIMER_ENABLE | flags, timer->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) static void rk_timer_update_counter(unsigned long cycles,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 				    struct rk_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	writel_relaxed(cycles, timer->base + TIMER_LOAD_COUNT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	writel_relaxed(0, timer->base + TIMER_LOAD_COUNT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static void rk_timer_interrupt_clear(struct rk_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	writel_relaxed(1, timer->base + TIMER_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static inline int rk_timer_set_next_event(unsigned long cycles,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 					  struct clock_event_device *ce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	struct rk_timer *timer = rk_timer(ce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	rk_timer_disable(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	rk_timer_update_counter(cycles, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	rk_timer_enable(timer, TIMER_MODE_USER_DEFINED_COUNT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 			       TIMER_INT_UNMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static int rk_timer_shutdown(struct clock_event_device *ce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	struct rk_timer *timer = rk_timer(ce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	rk_timer_disable(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int rk_timer_set_periodic(struct clock_event_device *ce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	struct rk_timer *timer = rk_timer(ce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	rk_timer_disable(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	rk_timer_update_counter(timer->freq / HZ - 1, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	rk_timer_enable(timer, TIMER_MODE_FREE_RUNNING | TIMER_INT_UNMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static irqreturn_t rk_timer_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	struct clock_event_device *ce = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	struct rk_timer *timer = rk_timer(ce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	rk_timer_interrupt_clear(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	if (clockevent_state_oneshot(ce))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		rk_timer_disable(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	ce->event_handler(ce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #ifndef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static u64 notrace rk_timer_sched_read(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	return ~readl_relaxed(rk_clksrc->base + TIMER_CURRENT_VALUE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) rk_timer_probe(struct rk_timer *timer, struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct clk *timer_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	int ret = -EINVAL, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	u32 ctrl_reg = TIMER_CONTROL_REG3288;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	timer->base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	if (!timer->base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		pr_err("Failed to get base address for '%s'\n", TIMER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	if (of_device_is_compatible(np, "rockchip,rk3399-timer"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		ctrl_reg = TIMER_CONTROL_REG3399;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	timer->ctrl = timer->base + ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	pclk = of_clk_get_by_name(np, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	if (IS_ERR(pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		ret = PTR_ERR(pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		pr_err("Failed to get pclk for '%s'\n", TIMER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		goto out_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	ret = clk_prepare_enable(pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		pr_err("Failed to enable pclk for '%s'\n", TIMER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		goto out_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	timer->pclk = pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	timer_clk = of_clk_get_by_name(np, "timer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	if (IS_ERR(timer_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		ret = PTR_ERR(timer_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		pr_err("Failed to get timer clock for '%s'\n", TIMER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		goto out_timer_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	ret = clk_prepare_enable(timer_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		pr_err("Failed to enable timer clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		goto out_timer_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	timer->clk = timer_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	timer->freq = clk_get_rate(timer_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	irq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	if (!irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		pr_err("Failed to map interrupts for '%s'\n", TIMER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		goto out_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	timer->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	rk_timer_interrupt_clear(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	rk_timer_disable(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) out_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	clk_disable_unprepare(timer_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) out_timer_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	clk_disable_unprepare(pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) out_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	iounmap(timer->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static void __init rk_timer_cleanup(struct rk_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	clk_disable_unprepare(timer->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	clk_disable_unprepare(timer->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	iounmap(timer->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static int __init rk_clkevt_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	struct clock_event_device *ce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	rk_clkevt = kzalloc(sizeof(struct rk_clkevt), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	if (!rk_clkevt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	ret = rk_timer_probe(&rk_clkevt->timer, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		goto out_probe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	ce = &rk_clkevt->ce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	ce->name = TIMER_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	ce->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		       CLOCK_EVT_FEAT_DYNIRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	ce->set_next_event = rk_timer_set_next_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	ce->set_state_shutdown = rk_timer_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	ce->set_state_periodic = rk_timer_set_periodic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	ce->irq = rk_clkevt->timer.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	ce->cpumask = cpu_possible_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	ce->rating = 250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	ret = request_irq(rk_clkevt->timer.irq, rk_timer_interrupt, IRQF_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			  TIMER_NAME, ce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		pr_err("Failed to initialize '%s': %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			TIMER_NAME, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		goto out_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	clockevents_config_and_register(&rk_clkevt->ce,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 					rk_clkevt->timer.freq, 1, UINT_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) out_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	rk_timer_cleanup(&rk_clkevt->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) out_probe:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	kfree(rk_clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	/* Leave rk_clkevt not NULL to prevent future init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	rk_clkevt = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #ifndef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static int __init rk_clksrc_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	rk_clksrc = kzalloc(sizeof(struct rk_timer), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	if (!rk_clksrc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	ret = rk_timer_probe(rk_clksrc, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		goto out_probe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	rk_timer_update_counter(UINT_MAX, rk_clksrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	rk_timer_enable(rk_clksrc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	ret = clocksource_mmio_init(rk_clksrc->base + TIMER_CURRENT_VALUE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		TIMER_NAME, rk_clksrc->freq, 250, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		clocksource_mmio_readl_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		pr_err("Failed to register clocksource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		goto out_clocksource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	sched_clock_register(rk_timer_sched_read, 32, rk_clksrc->freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) out_clocksource:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	rk_timer_cleanup(rk_clksrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) out_probe:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	kfree(rk_clksrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	/* Leave rk_clksrc not NULL to prevent future init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	rk_clksrc = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static int __init rk_timer_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	if (!rk_clkevt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		return rk_clkevt_init(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #ifndef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	if (!rk_clksrc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		return rk_clksrc_init(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	pr_err("Too many timer definitions for '%s'\n", TIMER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) TIMER_OF_DECLARE(rk3288_timer, "rockchip,rk3288-timer", rk_timer_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) TIMER_OF_DECLARE(rk3399_timer, "rockchip,rk3399-timer", rk_timer_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #ifdef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int __init rk_timer_driver_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	return rk_timer_init(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static const struct of_device_id rk_timer_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	{ .compatible = "rockchip,rk3288-timer" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	{ .compatible = "rockchip,rk3399-timer" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	{ /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static struct platform_driver rk_timer_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		.name = TIMER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		.of_match_table = rk_timer_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) module_platform_driver_probe(rk_timer_driver, rk_timer_driver_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #endif