^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * RDA8810PL SoC timer driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright RDA Microelectronics Company Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2017 Andreas Färber
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2018 Manivannan Sadhasivam
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * RDA8810PL has two independent timers: OSTIMER (56 bit) and HWTIMER (64 bit).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Each timer provides optional interrupt support. In this driver, OSTIMER is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * used for clockevents and HWTIMER is used for clocksource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "timer-of.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RDA_OSTIMER_LOADVAL_L 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RDA_OSTIMER_CTRL 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RDA_HWTIMER_LOCKVAL_L 0x024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RDA_HWTIMER_LOCKVAL_H 0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RDA_TIMER_IRQ_MASK_SET 0x02c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RDA_TIMER_IRQ_MASK_CLR 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RDA_TIMER_IRQ_CLR 0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RDA_OSTIMER_CTRL_ENABLE BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RDA_OSTIMER_CTRL_REPEAT BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RDA_OSTIMER_CTRL_LOAD BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RDA_TIMER_IRQ_MASK_OSTIMER BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RDA_TIMER_IRQ_CLR_OSTIMER BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static int rda_ostimer_start(void __iomem *base, bool periodic, u64 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u32 ctrl, load_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) load_l = (u32)cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ctrl = ((cycles >> 32) & 0xffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) ctrl |= RDA_OSTIMER_CTRL_LOAD | RDA_OSTIMER_CTRL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (periodic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) ctrl |= RDA_OSTIMER_CTRL_REPEAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Enable ostimer interrupt first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) writel_relaxed(RDA_TIMER_IRQ_MASK_OSTIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) base + RDA_TIMER_IRQ_MASK_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Write low 32 bits first, high 24 bits are with ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) writel_relaxed(load_l, base + RDA_OSTIMER_LOADVAL_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) writel_relaxed(ctrl, base + RDA_OSTIMER_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static int rda_ostimer_stop(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Disable ostimer interrupt first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) writel_relaxed(RDA_TIMER_IRQ_MASK_OSTIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) base + RDA_TIMER_IRQ_MASK_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) writel_relaxed(0, base + RDA_OSTIMER_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static int rda_ostimer_set_state_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct timer_of *to = to_timer_of(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) rda_ostimer_stop(timer_of_base(to));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static int rda_ostimer_set_state_oneshot(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct timer_of *to = to_timer_of(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) rda_ostimer_stop(timer_of_base(to));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static int rda_ostimer_set_state_periodic(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct timer_of *to = to_timer_of(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned long cycles_per_jiffy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) rda_ostimer_stop(timer_of_base(to));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) cycles_per_jiffy = ((unsigned long long)NSEC_PER_SEC / HZ *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) evt->mult) >> evt->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) rda_ostimer_start(timer_of_base(to), true, cycles_per_jiffy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static int rda_ostimer_tick_resume(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int rda_ostimer_set_next_event(unsigned long evt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct clock_event_device *ev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct timer_of *to = to_timer_of(ev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) rda_ostimer_start(timer_of_base(to), false, evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static irqreturn_t rda_ostimer_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct clock_event_device *evt = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct timer_of *to = to_timer_of(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* clear timer int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) writel_relaxed(RDA_TIMER_IRQ_CLR_OSTIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) timer_of_base(to) + RDA_TIMER_IRQ_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (evt->event_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) evt->event_handler(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static struct timer_of rda_ostimer_of = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .flags = TIMER_OF_IRQ | TIMER_OF_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .clkevt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .name = "rda-ostimer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .rating = 250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) CLOCK_EVT_FEAT_DYNIRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .set_state_shutdown = rda_ostimer_set_state_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .set_state_oneshot = rda_ostimer_set_state_oneshot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .set_state_periodic = rda_ostimer_set_state_periodic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .tick_resume = rda_ostimer_tick_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .set_next_event = rda_ostimer_set_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .of_base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .name = "rda-timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .index = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .of_irq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .name = "ostimer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .handler = rda_ostimer_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .flags = IRQF_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static u64 rda_hwtimer_read(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) void __iomem *base = timer_of_base(&rda_ostimer_of);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u32 lo, hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Always read low 32 bits first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) lo = readl_relaxed(base + RDA_HWTIMER_LOCKVAL_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) hi = readl_relaxed(base + RDA_HWTIMER_LOCKVAL_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) } while (hi != readl_relaxed(base + RDA_HWTIMER_LOCKVAL_H));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return ((u64)hi << 32) | lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static struct clocksource rda_hwtimer_clocksource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .name = "rda-timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .rating = 400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .read = rda_hwtimer_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .mask = CLOCKSOURCE_MASK(64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .flags = CLOCK_SOURCE_IS_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int __init rda_timer_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned long rate = 2000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ret = timer_of_init(np, &rda_ostimer_of);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) clocksource_register_hz(&rda_hwtimer_clocksource, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) clockevents_config_and_register(&rda_ostimer_of.clkevt, rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 0x2, UINT_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) TIMER_OF_DECLARE(rda8810pl, "rda,8810pl-timer", rda_timer_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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