Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2007 Google, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2009-2012,2014, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define TIMER_MATCH_VAL			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define TIMER_COUNT_VAL			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define TIMER_ENABLE			0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define TIMER_ENABLE_CLR_ON_MATCH_EN	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define TIMER_ENABLE_EN			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define TIMER_CLEAR			0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define DGT_CLK_CTL			0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define DGT_CLK_CTL_DIV_4		0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define TIMER_STS_GPT0_CLR_PEND		BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define GPT_HZ 32768
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) static void __iomem *event_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) static void __iomem *sts_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	struct clock_event_device *evt = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	/* Stop the timer tick */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	if (clockevent_state_oneshot(evt)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		ctrl &= ~TIMER_ENABLE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		writel_relaxed(ctrl, event_base + TIMER_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	evt->event_handler(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static int msm_timer_set_next_event(unsigned long cycles,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 				    struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	ctrl &= ~TIMER_ENABLE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	writel_relaxed(ctrl, event_base + TIMER_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	writel_relaxed(ctrl, event_base + TIMER_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	if (sts_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 			cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) static int msm_timer_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	ctrl = readl_relaxed(event_base + TIMER_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	writel_relaxed(ctrl, event_base + TIMER_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static struct clock_event_device __percpu *msm_evt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static void __iomem *source_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static notrace u64 msm_read_timer_count(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	return readl_relaxed(source_base + TIMER_COUNT_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static struct clocksource msm_clocksource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	.name	= "dg_timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	.rating	= 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	.read	= msm_read_timer_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	.mask	= CLOCKSOURCE_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static int msm_timer_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static int msm_timer_has_ppi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) static int msm_local_timer_starting_cpu(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	struct clock_event_device *evt = per_cpu_ptr(msm_evt, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	evt->irq = msm_timer_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	evt->name = "msm_timer";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	evt->features = CLOCK_EVT_FEAT_ONESHOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	evt->rating = 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	evt->set_state_shutdown = msm_timer_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	evt->set_state_oneshot = msm_timer_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	evt->tick_resume = msm_timer_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	evt->set_next_event = msm_timer_set_next_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	evt->cpumask = cpumask_of(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	clockevents_config_and_register(evt, GPT_HZ, 4, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	if (msm_timer_has_ppi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		err = request_irq(evt->irq, msm_timer_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 				IRQF_TIMER | IRQF_NOBALANCING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 				IRQF_TRIGGER_RISING, "gp_timer", evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			pr_err("request_irq failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int msm_local_timer_dying_cpu(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	struct clock_event_device *evt = per_cpu_ptr(msm_evt, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	evt->set_state_shutdown(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	disable_percpu_irq(evt->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static u64 notrace msm_sched_clock_read(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	return msm_clocksource.read(&msm_clocksource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static unsigned long msm_read_current_timer(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	return msm_clocksource.read(&msm_clocksource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static struct delay_timer msm_delay_timer = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	.read_current_timer = msm_read_current_timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 				  bool percpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	struct clocksource *cs = &msm_clocksource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	int res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	msm_timer_irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	msm_timer_has_ppi = percpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	msm_evt = alloc_percpu(struct clock_event_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	if (!msm_evt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		pr_err("memory allocation failed for clockevents\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	if (percpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		res = request_percpu_irq(irq, msm_timer_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 					 "gp_timer", msm_evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		pr_err("request_percpu_irq failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		/* Install and invoke hotplug callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		res = cpuhp_setup_state(CPUHP_AP_QCOM_TIMER_STARTING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 					"clockevents/qcom/timer:starting",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 					msm_local_timer_starting_cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 					msm_local_timer_dying_cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			free_percpu_irq(irq, msm_evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	res = clocksource_register_hz(cs, dgt_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		pr_err("clocksource_register failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	msm_delay_timer.freq = dgt_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	register_current_timer_delay(&msm_delay_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int __init msm_dt_timer_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	u32 freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	u32 percpu_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	void __iomem *cpu0_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		pr_err("Failed to map event base\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	/* We use GPT0 for the clockevent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	irq = irq_of_parse_and_map(np, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	if (irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		pr_err("Can't get irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	/* We use CPU0's DGT for the clocksource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		percpu_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	ret = of_address_to_resource(np, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		pr_err("Failed to parse DGT resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	if (!cpu0_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		pr_err("Failed to map source base\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	if (of_property_read_u32(np, "clock-frequency", &freq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		pr_err("Unknown frequency\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	event_base = base + 0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	sts_base = base + 0x88;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	source_base = cpu0_base + 0x24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	freq /= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	return msm_timer_init(freq, 32, irq, !!percpu_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) TIMER_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) TIMER_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);