^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * System timer for CSR SiRFprimaII
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PRIMA2_CLOCK_FREQ 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SIRFSOC_TIMER_COUNTER_LO 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SIRFSOC_TIMER_COUNTER_HI 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SIRFSOC_TIMER_MATCH_0 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SIRFSOC_TIMER_MATCH_1 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SIRFSOC_TIMER_MATCH_2 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SIRFSOC_TIMER_MATCH_3 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SIRFSOC_TIMER_MATCH_4 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SIRFSOC_TIMER_MATCH_5 0x001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SIRFSOC_TIMER_STATUS 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SIRFSOC_TIMER_INT_EN 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SIRFSOC_TIMER_WATCHDOG_EN 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SIRFSOC_TIMER_DIV 0x002C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SIRFSOC_TIMER_LATCH 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SIRFSOC_TIMER_LATCHED_LO 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SIRFSOC_TIMER_LATCHED_HI 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SIRFSOC_TIMER_WDT_INDEX 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SIRFSOC_TIMER_LATCH_BIT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SIRFSOC_TIMER_REG_CNT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) SIRFSOC_TIMER_MATCH_0, SIRFSOC_TIMER_MATCH_1, SIRFSOC_TIMER_MATCH_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) SIRFSOC_TIMER_MATCH_3, SIRFSOC_TIMER_MATCH_4, SIRFSOC_TIMER_MATCH_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) SIRFSOC_TIMER_INT_EN, SIRFSOC_TIMER_WATCHDOG_EN, SIRFSOC_TIMER_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) SIRFSOC_TIMER_LATCHED_LO, SIRFSOC_TIMER_LATCHED_HI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static void __iomem *sirfsoc_timer_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* timer0 interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct clock_event_device *ce = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) WARN_ON(!(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_STATUS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) BIT(0)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* clear timer0 interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ce->event_handler(ce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* read 64-bit timer counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static u64 notrace sirfsoc_timer_read(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u64 cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* latch the 64-bit timer counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) cycles = (cycles << 32) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static int sirfsoc_timer_set_next_event(unsigned long delta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct clock_event_device *ce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned long now, next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) next = now + delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) writel_relaxed(next, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return next - now > delta ? -ETIME : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int sirfsoc_timer_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) writel_relaxed(val & ~BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static int sirfsoc_timer_set_oneshot(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) writel_relaxed(val | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static void sirfsoc_clocksource_suspend(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) sirfsoc_timer_reg_val[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) readl_relaxed(sirfsoc_timer_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) sirfsoc_timer_reg_list[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static void sirfsoc_clocksource_resume(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) writel_relaxed(sirfsoc_timer_reg_val[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static struct clock_event_device sirfsoc_clockevent = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .name = "sirfsoc_clockevent",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .rating = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .features = CLOCK_EVT_FEAT_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .set_state_shutdown = sirfsoc_timer_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .set_state_oneshot = sirfsoc_timer_set_oneshot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .set_next_event = sirfsoc_timer_set_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static struct clocksource sirfsoc_clocksource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .name = "sirfsoc_clocksource",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .rating = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .mask = CLOCKSOURCE_MASK(64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .flags = CLOCK_SOURCE_IS_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .read = sirfsoc_timer_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .suspend = sirfsoc_clocksource_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .resume = sirfsoc_clocksource_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* Overwrite weak default sched_clock with more precise one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static u64 notrace sirfsoc_read_sched_clock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return sirfsoc_timer_read(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static void __init sirfsoc_clockevent_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) sirfsoc_clockevent.cpumask = cpumask_of(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) clockevents_config_and_register(&sirfsoc_clockevent, PRIMA2_CLOCK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 2, -2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* initialize the kernel jiffy timer source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int __init sirfsoc_prima2_timer_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) clk = of_clk_get(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) pr_err("Failed to get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) pr_err("Failed to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (rate < PRIMA2_CLOCK_FREQ || rate % PRIMA2_CLOCK_FREQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) pr_err("Invalid clock rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) sirfsoc_timer_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (!sirfsoc_timer_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) pr_err("unable to map timer cpu registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) irq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) writel_relaxed(rate / PRIMA2_CLOCK_FREQ / 2 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) sirfsoc_timer_base + SIRFSOC_TIMER_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ret = clocksource_register_hz(&sirfsoc_clocksource, PRIMA2_CLOCK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) pr_err("Failed to register clocksource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) sched_clock_register(sirfsoc_read_sched_clock, 64, PRIMA2_CLOCK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ret = request_irq(irq, sirfsoc_timer_interrupt, IRQF_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) "sirfsoc_timer0", &sirfsoc_clockevent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) pr_err("Failed to setup irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) sirfsoc_clockevent_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) TIMER_OF_DECLARE(sirfsoc_prima2_timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) "sirf,prima2-tick", sirfsoc_prima2_timer_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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