Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Pistachio clocksource based on general-purpose timers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2015 Imagination Technologies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define pr_fmt(fmt) "%s: " fmt, __func__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* Top level reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define CR_TIMER_CTRL_CFG		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define TIMER_ME_GLOBAL			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define CR_TIMER_REV			0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /* Timer specific registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define TIMER_CFG			0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define TIMER_ME_LOCAL			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define TIMER_RELOAD_VALUE		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define TIMER_CURRENT_VALUE		0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define TIMER_CURRENT_OVERFLOW_VALUE	0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define TIMER_IRQ_STATUS		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define TIMER_IRQ_CLEAR			0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define TIMER_IRQ_MASK			0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define PERIP_TIMER_CONTROL		0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /* Timer specific configuration Values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define RELOAD_VALUE			0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) struct pistachio_clocksource {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	raw_spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	struct clocksource cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static struct pistachio_clocksource pcs_gpt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define to_pistachio_clocksource(cs)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	container_of(cs, struct pistachio_clocksource, cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static inline u32 gpt_readl(void __iomem *base, u32 offset, u32 gpt_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	return readl(base + 0x20 * gpt_id + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static inline void gpt_writel(void __iomem *base, u32 value, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		u32 gpt_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	writel(value, base + 0x20 * gpt_id + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) static u64 notrace
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) pistachio_clocksource_read_cycles(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	u32 counter, overflw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	 * The counter value is only refreshed after the overflow value is read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	 * And they must be read in strict order, hence raw spin lock added.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	raw_spin_lock_irqsave(&pcs->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	overflw = gpt_readl(pcs->base, TIMER_CURRENT_OVERFLOW_VALUE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	counter = gpt_readl(pcs->base, TIMER_CURRENT_VALUE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	raw_spin_unlock_irqrestore(&pcs->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	return (u64)~counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static u64 notrace pistachio_read_sched_clock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	return pistachio_clocksource_read_cycles(&pcs_gpt.cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static void pistachio_clksrc_set_mode(struct clocksource *cs, int timeridx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 			int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	val = gpt_readl(pcs->base, TIMER_CFG, timeridx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		val |= TIMER_ME_LOCAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		val &= ~TIMER_ME_LOCAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	gpt_writel(pcs->base, val, TIMER_CFG, timeridx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static void pistachio_clksrc_enable(struct clocksource *cs, int timeridx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	/* Disable GPT local before loading reload value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	pistachio_clksrc_set_mode(cs, timeridx, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	gpt_writel(pcs->base, RELOAD_VALUE, TIMER_RELOAD_VALUE, timeridx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	pistachio_clksrc_set_mode(cs, timeridx, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void pistachio_clksrc_disable(struct clocksource *cs, int timeridx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	/* Disable GPT local */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	pistachio_clksrc_set_mode(cs, timeridx, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int pistachio_clocksource_enable(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	pistachio_clksrc_enable(cs, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static void pistachio_clocksource_disable(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	pistachio_clksrc_disable(cs, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Desirable clock source for pistachio platform */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static struct pistachio_clocksource pcs_gpt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.cs =	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		.name		= "gptimer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		.rating		= 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		.enable		= pistachio_clocksource_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		.disable	= pistachio_clocksource_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		.read		= pistachio_clocksource_read_cycles,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		.mask		= CLOCKSOURCE_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		.flags		= CLOCK_SOURCE_IS_CONTINUOUS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 				  CLOCK_SOURCE_SUSPEND_NONSTOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int __init pistachio_clksrc_of_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	struct clk *sys_clk, *fast_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	struct regmap *periph_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	pcs_gpt.base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	if (!pcs_gpt.base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		pr_err("cannot iomap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	periph_regs = syscon_regmap_lookup_by_phandle(node, "img,cr-periph");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	if (IS_ERR(periph_regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		pr_err("cannot get peripheral regmap (%ld)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		       PTR_ERR(periph_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		return PTR_ERR(periph_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	/* Switch to using the fast counter clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	ret = regmap_update_bits(periph_regs, PERIP_TIMER_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 				 0xf, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	sys_clk = of_clk_get_by_name(node, "sys");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	if (IS_ERR(sys_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		pr_err("clock get failed (%ld)\n", PTR_ERR(sys_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		return PTR_ERR(sys_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	fast_clk = of_clk_get_by_name(node, "fast");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	if (IS_ERR(fast_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		pr_err("clock get failed (%lu)\n", PTR_ERR(fast_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		return PTR_ERR(fast_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	ret = clk_prepare_enable(sys_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		pr_err("failed to enable clock (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	ret = clk_prepare_enable(fast_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		pr_err("failed to enable clock (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		clk_disable_unprepare(sys_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	rate = clk_get_rate(fast_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	/* Disable irq's for clocksource usage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	gpt_writel(pcs_gpt.base, 0, TIMER_IRQ_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	gpt_writel(pcs_gpt.base, 0, TIMER_IRQ_MASK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	gpt_writel(pcs_gpt.base, 0, TIMER_IRQ_MASK, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	gpt_writel(pcs_gpt.base, 0, TIMER_IRQ_MASK, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	/* Enable timer block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	writel(TIMER_ME_GLOBAL, pcs_gpt.base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	raw_spin_lock_init(&pcs_gpt.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	sched_clock_register(pistachio_read_sched_clock, 32, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	return clocksource_register_hz(&pcs_gpt.cs, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) TIMER_OF_DECLARE(pistachio_gptimer, "img,pistachio-gptimer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		       pistachio_clksrc_of_init);