Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * drivers/clocksource/timer-oxnas-rps.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2009 Oxford Semiconductor Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /* TIMER1 used as tick
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * TIMER2 used as clocksource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /* Registers definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define TIMER_LOAD_REG		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define TIMER_CURR_REG		0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define TIMER_CTRL_REG		0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define TIMER_CLRINT_REG	0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define TIMER_BITS		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define TIMER_MAX_VAL		(BIT(TIMER_BITS) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define TIMER_PERIODIC		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define TIMER_ENABLE		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define TIMER_DIV1		(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define TIMER_DIV16		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define TIMER_DIV256		(2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define TIMER1_REG_OFFSET	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define TIMER2_REG_OFFSET	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) /* Clockevent & Clocksource data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) struct oxnas_rps_timer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	struct clock_event_device clkevent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	void __iomem *clksrc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	void __iomem *clkevt_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	unsigned long timer_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	unsigned int timer_prescaler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static irqreturn_t oxnas_rps_timer_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	struct oxnas_rps_timer *rps = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	writel_relaxed(0, rps->clkevt_base + TIMER_CLRINT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	rps->clkevent.event_handler(&rps->clkevent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) static void oxnas_rps_timer_config(struct oxnas_rps_timer *rps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 				   unsigned long period,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 				   unsigned int periodic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	uint32_t cfg = rps->timer_prescaler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	if (period)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		cfg |= TIMER_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	if (periodic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		cfg |= TIMER_PERIODIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	writel_relaxed(period, rps->clkevt_base + TIMER_LOAD_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	writel_relaxed(cfg, rps->clkevt_base + TIMER_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) static int oxnas_rps_timer_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	struct oxnas_rps_timer *rps =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		container_of(evt, struct oxnas_rps_timer, clkevent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	oxnas_rps_timer_config(rps, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static int oxnas_rps_timer_set_periodic(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	struct oxnas_rps_timer *rps =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		container_of(evt, struct oxnas_rps_timer, clkevent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	oxnas_rps_timer_config(rps, rps->timer_period, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int oxnas_rps_timer_set_oneshot(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	struct oxnas_rps_timer *rps =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		container_of(evt, struct oxnas_rps_timer, clkevent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	oxnas_rps_timer_config(rps, rps->timer_period, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int oxnas_rps_timer_next_event(unsigned long delta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 				struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	struct oxnas_rps_timer *rps =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		container_of(evt, struct oxnas_rps_timer, clkevent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	oxnas_rps_timer_config(rps, delta, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int __init oxnas_rps_clockevent_init(struct oxnas_rps_timer *rps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	ulong clk_rate = clk_get_rate(rps->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	ulong timer_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	/* Start with prescaler 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	rps->timer_prescaler = TIMER_DIV1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	rps->timer_period = DIV_ROUND_UP(clk_rate, HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	timer_rate = clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	if (rps->timer_period > TIMER_MAX_VAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		rps->timer_prescaler = TIMER_DIV16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		timer_rate = clk_rate / 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		rps->timer_period = DIV_ROUND_UP(timer_rate, HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	if (rps->timer_period > TIMER_MAX_VAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		rps->timer_prescaler = TIMER_DIV256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		timer_rate = clk_rate / 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		rps->timer_period = DIV_ROUND_UP(timer_rate, HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	rps->clkevent.name = "oxnas-rps";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	rps->clkevent.features = CLOCK_EVT_FEAT_PERIODIC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 				 CLOCK_EVT_FEAT_ONESHOT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 				 CLOCK_EVT_FEAT_DYNIRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	rps->clkevent.tick_resume = oxnas_rps_timer_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	rps->clkevent.set_state_shutdown = oxnas_rps_timer_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	rps->clkevent.set_state_periodic = oxnas_rps_timer_set_periodic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	rps->clkevent.set_state_oneshot = oxnas_rps_timer_set_oneshot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	rps->clkevent.set_next_event = oxnas_rps_timer_next_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	rps->clkevent.rating = 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	rps->clkevent.cpumask = cpu_possible_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	rps->clkevent.irq = rps->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	clockevents_config_and_register(&rps->clkevent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 					timer_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 					1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 					TIMER_MAX_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	pr_info("Registered clock event rate %luHz prescaler %x period %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			clk_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 			rps->timer_prescaler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			rps->timer_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Clocksource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static void __iomem *timer_sched_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static u64 notrace oxnas_rps_read_sched_clock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	return ~readl_relaxed(timer_sched_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static int __init oxnas_rps_clocksource_init(struct oxnas_rps_timer *rps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	ulong clk_rate = clk_get_rate(rps->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	/* use prescale 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	clk_rate = clk_rate / 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	writel_relaxed(TIMER_MAX_VAL, rps->clksrc_base + TIMER_LOAD_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	writel_relaxed(TIMER_PERIODIC | TIMER_ENABLE | TIMER_DIV16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			rps->clksrc_base + TIMER_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	timer_sched_base = rps->clksrc_base + TIMER_CURR_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	sched_clock_register(oxnas_rps_read_sched_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 			     TIMER_BITS, clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	ret = clocksource_mmio_init(timer_sched_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 				    "oxnas_rps_clocksource_timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 				    clk_rate, 250, TIMER_BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 				    clocksource_mmio_readl_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	if (WARN_ON(ret)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		pr_err("can't register clocksource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	pr_info("Registered clocksource rate %luHz\n", clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int __init oxnas_rps_timer_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	struct oxnas_rps_timer *rps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	rps = kzalloc(sizeof(*rps), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	if (!rps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	rps->clk = of_clk_get(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	if (IS_ERR(rps->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		ret = PTR_ERR(rps->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		goto err_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	ret = clk_prepare_enable(rps->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		goto err_clk_prepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	rps->irq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	if (rps->irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		goto err_iomap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	rps->clkevt_base = base + TIMER1_REG_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	rps->clksrc_base = base + TIMER2_REG_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	/* Disable timers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	writel_relaxed(0, rps->clkevt_base + TIMER_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	writel_relaxed(0, rps->clksrc_base + TIMER_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	writel_relaxed(0, rps->clkevt_base + TIMER_LOAD_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	writel_relaxed(0, rps->clksrc_base + TIMER_LOAD_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	writel_relaxed(0, rps->clkevt_base + TIMER_CLRINT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	writel_relaxed(0, rps->clksrc_base + TIMER_CLRINT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	ret = request_irq(rps->irq, oxnas_rps_timer_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 			  IRQF_TIMER | IRQF_IRQPOLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 			  "rps-timer", rps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		goto err_iomap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	ret = oxnas_rps_clocksource_init(rps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		goto err_irqreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	ret = oxnas_rps_clockevent_init(rps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		goto err_irqreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) err_irqreq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	free_irq(rps->irq, rps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) err_iomap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) err_clk_prepare:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	clk_disable_unprepare(rps->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	clk_put(rps->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) err_alloc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	kfree(rps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) TIMER_OF_DECLARE(ox810se_rps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		       "oxsemi,ox810se-rps-timer", oxnas_rps_timer_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) TIMER_OF_DECLARE(ox820_rps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		       "oxsemi,ox820-rps-timer", oxnas_rps_timer_init);