^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This software is available to you under a choice of one of two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * licenses. You may choose to be licensed under the terms of the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * General Public License (GPL) Version 2, available from the file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * COPYING in the main directory of this source tree, or the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * OpenIB.org BSD license below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Redistribution and use in source and binary forms, with or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * without modification, are permitted provided that the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * conditions are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * - Redistributions of source code must retain the above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * copyright notice, this list of conditions and the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * - Redistributions in binary form must reproduce the above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * copyright notice, this list of conditions and the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * disclaimer in the documentation and/or other materials
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * provided with the distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <soc/nps/common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define NPS_MSU_TICK_LOW 0xC8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define NPS_CLUSTER_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define NPS_CLUSTER_NUM 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* This array is per cluster of CPUs (Each NPS400 cluster got 256 CPUs) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static void *nps_msu_reg_low_addr[NPS_CLUSTER_NUM] __read_mostly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static int __init nps_get_timer_clk(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned long *timer_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct clk **clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) *clk = of_clk_get(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ret = PTR_ERR_OR_ZERO(*clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) pr_err("timer missing clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ret = clk_prepare_enable(*clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) pr_err("Couldn't enable parent clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) clk_put(*clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) *timer_freq = clk_get_rate(*clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (!(*timer_freq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) pr_err("Couldn't get clk rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) clk_disable_unprepare(*clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) clk_put(*clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static u64 nps_clksrc_read(struct clocksource *clksrc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int cluster = raw_smp_processor_id() >> NPS_CLUSTER_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return (u64)ioread32be(nps_msu_reg_low_addr[cluster]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static int __init nps_setup_clocksource(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int ret, cluster;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned long nps_timer1_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) for (cluster = 0; cluster < NPS_CLUSTER_NUM; cluster++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) nps_msu_reg_low_addr[cluster] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) nps_host_reg((cluster << NPS_CLUSTER_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) NPS_MSU_BLKID, NPS_MSU_TICK_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ret = nps_get_timer_clk(node, &nps_timer1_freq, &clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ret = clocksource_mmio_init(nps_msu_reg_low_addr, "nps-tick",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) nps_timer1_freq, 300, 32, nps_clksrc_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) pr_err("Couldn't register clock source.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) TIMER_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) nps_setup_clocksource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) TIMER_OF_DECLARE(ezchip_nps400_clk_src, "ezchip,nps400-timer1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) nps_setup_clocksource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #ifdef CONFIG_EZNPS_MTM_EXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #include <soc/nps/mtm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Timer related Aux registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define NPS_REG_TIMER0_TSI 0xFFFFF850
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define NPS_REG_TIMER0_LIMIT 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define NPS_REG_TIMER0_CTRL 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define NPS_REG_TIMER0_CNT 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * Interrupt Enabled (IE) - re-arm the timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * Not Halted (NH) - is cleared when working with JTAG (for debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define TIMER0_CTRL_IE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define TIMER0_CTRL_NH BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static unsigned long nps_timer0_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static unsigned long nps_timer0_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static void nps_clkevent_rm_thread(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int thread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned int cflags, enabled_threads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) hw_schd_save(&cflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) enabled_threads = read_aux_reg(NPS_REG_TIMER0_TSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* remove thread from TSI1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) thread = read_aux_reg(CTOP_AUX_THREAD_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) enabled_threads &= ~(1 << thread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) write_aux_reg(NPS_REG_TIMER0_TSI, enabled_threads);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Acknowledge and if needed re-arm the timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (!enabled_threads)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) write_aux_reg(NPS_REG_TIMER0_CTRL, TIMER0_CTRL_NH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) write_aux_reg(NPS_REG_TIMER0_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) TIMER0_CTRL_IE | TIMER0_CTRL_NH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) hw_schd_restore(cflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static void nps_clkevent_add_thread(unsigned long delta)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int thread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned int cflags, enabled_threads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) hw_schd_save(&cflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* add thread to TSI1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) thread = read_aux_reg(CTOP_AUX_THREAD_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) enabled_threads = read_aux_reg(NPS_REG_TIMER0_TSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) enabled_threads |= (1 << thread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) write_aux_reg(NPS_REG_TIMER0_TSI, enabled_threads);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* set next timer event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) write_aux_reg(NPS_REG_TIMER0_LIMIT, delta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) write_aux_reg(NPS_REG_TIMER0_CNT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) write_aux_reg(NPS_REG_TIMER0_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) TIMER0_CTRL_IE | TIMER0_CTRL_NH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) hw_schd_restore(cflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * Whenever anyone tries to change modes, we just mask interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * and wait for the next event to get set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static int nps_clkevent_set_state(struct clock_event_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) nps_clkevent_rm_thread();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) disable_percpu_irq(nps_timer0_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int nps_clkevent_set_next_event(unsigned long delta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct clock_event_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) nps_clkevent_add_thread(delta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) enable_percpu_irq(nps_timer0_irq, IRQ_TYPE_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static DEFINE_PER_CPU(struct clock_event_device, nps_clockevent_device) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .name = "NPS Timer0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .features = CLOCK_EVT_FEAT_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .rating = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .set_next_event = nps_clkevent_set_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .set_state_oneshot = nps_clkevent_set_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .set_state_oneshot_stopped = nps_clkevent_set_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .set_state_shutdown = nps_clkevent_set_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .tick_resume = nps_clkevent_set_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static irqreturn_t timer_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct clock_event_device *evt = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) nps_clkevent_rm_thread();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) evt->event_handler(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static int nps_timer_starting_cpu(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct clock_event_device *evt = this_cpu_ptr(&nps_clockevent_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) evt->cpumask = cpumask_of(smp_processor_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) clockevents_config_and_register(evt, nps_timer0_freq, 0, ULONG_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) enable_percpu_irq(nps_timer0_irq, IRQ_TYPE_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static int nps_timer_dying_cpu(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) disable_percpu_irq(nps_timer0_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int __init nps_setup_clockevent(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) nps_timer0_irq = irq_of_parse_and_map(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (nps_timer0_irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) pr_err("clockevent: missing irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ret = nps_get_timer_clk(node, &nps_timer0_freq, &clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* Needs apriori irq_set_percpu_devid() done in intc map function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ret = request_percpu_irq(nps_timer0_irq, timer_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) "Timer0 (per-cpu-tick)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) &nps_clockevent_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) pr_err("Couldn't request irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ret = cpuhp_setup_state(CPUHP_AP_ARC_TIMER_STARTING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) "clockevents/nps:starting",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) nps_timer_starting_cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) nps_timer_dying_cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) pr_err("Failed to setup hotplug state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) free_percpu_irq(nps_timer0_irq, &nps_clockevent_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) TIMER_OF_DECLARE(ezchip_nps400_clk_evt, "ezchip,nps400-timer0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) nps_setup_clockevent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #endif /* CONFIG_EZNPS_MTM_EXT */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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