^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2014-2018 Nuvoton Technologies tomer.maimon@nuvoton.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2017 Google, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "timer-of.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Timers registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define NPCM7XX_REG_TCSR0 0x0 /* Timer 0 Control and Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define NPCM7XX_REG_TICR0 0x8 /* Timer 0 Initial Count Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define NPCM7XX_REG_TCSR1 0x4 /* Timer 1 Control and Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define NPCM7XX_REG_TICR1 0xc /* Timer 1 Initial Count Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define NPCM7XX_REG_TDR1 0x14 /* Timer 1 Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define NPCM7XX_REG_TISR 0x18 /* Timer Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* Timers control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define NPCM7XX_Tx_RESETINT 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define NPCM7XX_Tx_PERIOD BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define NPCM7XX_Tx_INTEN BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define NPCM7XX_Tx_COUNTEN BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define NPCM7XX_Tx_ONESHOT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define NPCM7XX_Tx_OPER GENMASK(28, 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define NPCM7XX_Tx_MIN_PRESCALE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define NPCM7XX_Tx_TDR_MASK_BITS 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define NPCM7XX_Tx_MAX_CNT 0xFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define NPCM7XX_T0_CLR_INT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define NPCM7XX_Tx_CLR_CSR 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* Timers operating mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define NPCM7XX_START_PERIODIC_Tx (NPCM7XX_Tx_PERIOD | NPCM7XX_Tx_COUNTEN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) NPCM7XX_Tx_INTEN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) NPCM7XX_Tx_MIN_PRESCALE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define NPCM7XX_START_ONESHOT_Tx (NPCM7XX_Tx_ONESHOT | NPCM7XX_Tx_COUNTEN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) NPCM7XX_Tx_INTEN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) NPCM7XX_Tx_MIN_PRESCALE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define NPCM7XX_START_Tx (NPCM7XX_Tx_COUNTEN | NPCM7XX_Tx_PERIOD | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) NPCM7XX_Tx_MIN_PRESCALE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define NPCM7XX_DEFAULT_CSR (NPCM7XX_Tx_CLR_CSR | NPCM7XX_Tx_MIN_PRESCALE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static int npcm7xx_timer_resume(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct timer_of *to = to_timer_of(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) val |= NPCM7XX_Tx_COUNTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static int npcm7xx_timer_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct timer_of *to = to_timer_of(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) val &= ~NPCM7XX_Tx_COUNTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static int npcm7xx_timer_oneshot(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct timer_of *to = to_timer_of(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) val &= ~NPCM7XX_Tx_OPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) val |= NPCM7XX_START_ONESHOT_Tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static int npcm7xx_timer_periodic(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct timer_of *to = to_timer_of(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) val &= ~NPCM7XX_Tx_OPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) val |= NPCM7XX_START_PERIODIC_Tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int npcm7xx_clockevent_set_next_event(unsigned long evt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct clock_event_device *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct timer_of *to = to_timer_of(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) writel(evt, timer_of_base(to) + NPCM7XX_REG_TICR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) val |= NPCM7XX_START_Tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static irqreturn_t npcm7xx_timer0_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct clock_event_device *evt = (struct clock_event_device *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct timer_of *to = to_timer_of(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) writel(NPCM7XX_T0_CLR_INT, timer_of_base(to) + NPCM7XX_REG_TISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) evt->event_handler(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static struct timer_of npcm7xx_to = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .clkevt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .name = "npcm7xx-timer0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .features = CLOCK_EVT_FEAT_PERIODIC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) CLOCK_EVT_FEAT_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .set_next_event = npcm7xx_clockevent_set_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .set_state_shutdown = npcm7xx_timer_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .set_state_periodic = npcm7xx_timer_periodic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .set_state_oneshot = npcm7xx_timer_oneshot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .tick_resume = npcm7xx_timer_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .rating = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .of_irq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .handler = npcm7xx_timer0_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .flags = IRQF_TIMER | IRQF_IRQPOLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static void __init npcm7xx_clockevents_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) writel(NPCM7XX_DEFAULT_CSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) writel(NPCM7XX_Tx_RESETINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) npcm7xx_to.clkevt.cpumask = cpumask_of(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) clockevents_config_and_register(&npcm7xx_to.clkevt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) timer_of_rate(&npcm7xx_to),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 0x1, NPCM7XX_Tx_MAX_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static void __init npcm7xx_clocksource_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) writel(NPCM7XX_DEFAULT_CSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) writel(NPCM7XX_Tx_MAX_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TICR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) val = readl(timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) val |= NPCM7XX_START_Tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) writel(val, timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) clocksource_mmio_init(timer_of_base(&npcm7xx_to) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) NPCM7XX_REG_TDR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) "npcm7xx-timer1", timer_of_rate(&npcm7xx_to),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 200, (unsigned int)NPCM7XX_Tx_TDR_MASK_BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) clocksource_mmio_readl_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int __init npcm7xx_timer_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ret = timer_of_init(np, &npcm7xx_to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Clock input is divided by PRESCALE + 1 before it is fed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* to the counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) npcm7xx_to.of_clk.rate = npcm7xx_to.of_clk.rate /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) (NPCM7XX_Tx_MIN_PRESCALE + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) npcm7xx_clocksource_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) npcm7xx_clockevents_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) pr_info("Enabling NPCM7xx clocksource timer base: %px, IRQ: %d ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) timer_of_base(&npcm7xx_to), timer_of_irq(&npcm7xx_to));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) TIMER_OF_DECLARE(npcm7xx, "nuvoton,npcm750-timer", npcm7xx_timer_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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