Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Amlogic Meson6 SoCs timer handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2014 Carlo Caione <carlo@caione.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Based on code from Amlogic, Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/irqreturn.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #ifdef CONFIG_ARM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define MESON_ISA_TIMER_MUX					0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define MESON_ISA_TIMER_MUX_TIMERD_EN				BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define MESON_ISA_TIMER_MUX_TIMERC_EN				BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define MESON_ISA_TIMER_MUX_TIMERB_EN				BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define MESON_ISA_TIMER_MUX_TIMERA_EN				BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define MESON_ISA_TIMER_MUX_TIMERD_MODE				BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define MESON_ISA_TIMER_MUX_TIMERC_MODE				BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define MESON_ISA_TIMER_MUX_TIMERB_MODE				BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define MESON_ISA_TIMER_MUX_TIMERA_MODE				BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_MASK		GENMASK(10, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_SYSTEM_CLOCK	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_1US		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_10US		0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_100US		0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_1MS		0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define MESON_ISA_TIMER_MUX_TIMERD_INPUT_CLOCK_MASK		GENMASK(7, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define MESON_ISA_TIMER_MUX_TIMERC_INPUT_CLOCK_MASK		GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define MESON_ISA_TIMER_MUX_TIMERB_INPUT_CLOCK_MASK		GENMASK(3, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define MESON_ISA_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK		GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_1US		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_10US		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_100US		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_1MS		0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define MESON_ISA_TIMERA					0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define MESON_ISA_TIMERB					0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define MESON_ISA_TIMERC					0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define MESON_ISA_TIMERD					0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define MESON_ISA_TIMERE					0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static void __iomem *timer_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #ifdef CONFIG_ARM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static unsigned long meson6_read_current_timer(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	return readl_relaxed(timer_base + MESON_ISA_TIMERE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static struct delay_timer meson6_delay_timer = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	.read_current_timer = meson6_read_current_timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	.freq = 1000 * 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) static u64 notrace meson6_timer_sched_read(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	return (u64)readl(timer_base + MESON_ISA_TIMERE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static void meson6_clkevt_time_stop(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	u32 val = readl(timer_base + MESON_ISA_TIMER_MUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	writel(val & ~MESON_ISA_TIMER_MUX_TIMERA_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	       timer_base + MESON_ISA_TIMER_MUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static void meson6_clkevt_time_setup(unsigned long delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	writel(delay, timer_base + MESON_ISA_TIMERA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static void meson6_clkevt_time_start(bool periodic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	u32 val = readl(timer_base + MESON_ISA_TIMER_MUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	if (periodic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		val |= MESON_ISA_TIMER_MUX_TIMERA_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		val &= ~MESON_ISA_TIMER_MUX_TIMERA_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	writel(val | MESON_ISA_TIMER_MUX_TIMERA_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	       timer_base + MESON_ISA_TIMER_MUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int meson6_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	meson6_clkevt_time_stop();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int meson6_set_oneshot(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	meson6_clkevt_time_stop();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	meson6_clkevt_time_start(false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static int meson6_set_periodic(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	meson6_clkevt_time_stop();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	meson6_clkevt_time_setup(USEC_PER_SEC / HZ - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	meson6_clkevt_time_start(true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int meson6_clkevt_next_event(unsigned long evt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 				    struct clock_event_device *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	meson6_clkevt_time_stop();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	meson6_clkevt_time_setup(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	meson6_clkevt_time_start(false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static struct clock_event_device meson6_clockevent = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	.name			= "meson6_tick",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	.rating			= 400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	.features		= CLOCK_EVT_FEAT_PERIODIC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 				  CLOCK_EVT_FEAT_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	.set_state_shutdown	= meson6_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	.set_state_periodic	= meson6_set_periodic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.set_state_oneshot	= meson6_set_oneshot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	.tick_resume		= meson6_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	.set_next_event		= meson6_clkevt_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static irqreturn_t meson6_timer_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	evt->event_handler(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int __init meson6_timer_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	timer_base = of_io_request_and_map(node, 0, "meson6-timer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	if (IS_ERR(timer_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		pr_err("Can't map registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	irq = irq_of_parse_and_map(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	if (irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		pr_err("Can't parse IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	/* Set 1us for timer E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	val = readl(timer_base + MESON_ISA_TIMER_MUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	val &= ~MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	val |= FIELD_PREP(MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			  MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_1US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	writel(val, timer_base + MESON_ISA_TIMER_MUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	sched_clock_register(meson6_timer_sched_read, 32, USEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	clocksource_mmio_init(timer_base + MESON_ISA_TIMERE, node->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			      1000 * 1000, 300, 32, clocksource_mmio_readl_up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	/* Timer A base 1us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	val &= ~MESON_ISA_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	val |= FIELD_PREP(MESON_ISA_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 			  MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_1US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	writel(val, timer_base + MESON_ISA_TIMER_MUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	/* Stop the timer A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	meson6_clkevt_time_stop();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	ret = request_irq(irq, meson6_timer_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			  IRQF_TIMER | IRQF_IRQPOLL, "meson6_timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			  &meson6_clockevent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		pr_warn("failed to setup irq %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	meson6_clockevent.cpumask = cpu_possible_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	meson6_clockevent.irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	clockevents_config_and_register(&meson6_clockevent, USEC_PER_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 					1, 0xfffe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #ifdef CONFIG_ARM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	/* Also use MESON_ISA_TIMERE for delays */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	register_current_timer_delay(&meson6_delay_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) TIMER_OF_DECLARE(meson6, "amlogic,meson6-timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		       meson6_timer_init);