^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Mediatek SoCs General-Purpose Timer handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 Matthias Brugger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Matthias Brugger <matthias.bgg@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/irqreturn.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "timer-of.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TIMER_CLK_EVT (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TIMER_CLK_SRC (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TIMER_SYNC_TICKS (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* gpt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define GPT_IRQ_EN_REG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define GPT_IRQ_ENABLE(val) BIT((val) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define GPT_IRQ_ACK_REG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define GPT_IRQ_ACK(val) BIT((val) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define GPT_CTRL_REG(val) (0x10 * (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define GPT_CTRL_OP(val) (((val) & 0x3) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define GPT_CTRL_OP_ONESHOT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define GPT_CTRL_OP_REPEAT (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define GPT_CTRL_OP_FREERUN (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define GPT_CTRL_CLEAR (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define GPT_CTRL_ENABLE (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define GPT_CTRL_DISABLE (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define GPT_CLK_REG(val) (0x04 + (0x10 * (val)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GPT_CLK_SRC(val) (((val) & 0x1) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GPT_CLK_SRC_SYS13M (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GPT_CLK_SRC_RTC32K (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define GPT_CLK_DIV1 (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GPT_CLK_DIV2 (0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GPT_CNT_REG(val) (0x08 + (0x10 * (val)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GPT_CMP_REG(val) (0x0C + (0x10 * (val)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* system timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SYST_BASE (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SYST_CON (SYST_BASE + 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SYST_VAL (SYST_BASE + 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SYST_CON_REG(to) (timer_of_base(to) + SYST_CON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SYST_VAL_REG(to) (timer_of_base(to) + SYST_VAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * SYST_CON_EN: Clock enable. Shall be set to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * - Start timer countdown.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * - Allow timeout ticks being updated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * - Allow changing interrupt functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * SYST_CON_IRQ_EN: Set to allow interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * SYST_CON_IRQ_CLR: Set to clear interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SYST_CON_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SYST_CON_IRQ_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SYST_CON_IRQ_CLR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static void __iomem *gpt_sched_reg __read_mostly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static void mtk_syst_ack_irq(struct timer_of *to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Clear and disable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) writel(SYST_CON_IRQ_CLR | SYST_CON_EN, SYST_CON_REG(to));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static irqreturn_t mtk_syst_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct clock_event_device *clkevt = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct timer_of *to = to_timer_of(clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) mtk_syst_ack_irq(to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) clkevt->event_handler(clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static int mtk_syst_clkevt_next_event(unsigned long ticks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct clock_event_device *clkevt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct timer_of *to = to_timer_of(clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Enable clock to allow timeout tick update later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) writel(SYST_CON_EN, SYST_CON_REG(to));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * Write new timeout ticks. Timer shall start countdown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * after timeout ticks are updated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) writel(ticks, SYST_VAL_REG(to));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Enable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) writel(SYST_CON_EN | SYST_CON_IRQ_EN, SYST_CON_REG(to));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static int mtk_syst_clkevt_shutdown(struct clock_event_device *clkevt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Disable timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) writel(0, SYST_CON_REG(to_timer_of(clkevt)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int mtk_syst_clkevt_resume(struct clock_event_device *clkevt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return mtk_syst_clkevt_shutdown(clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int mtk_syst_clkevt_oneshot(struct clock_event_device *clkevt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static u64 notrace mtk_gpt_read_sched_clock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return readl_relaxed(gpt_sched_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static void mtk_gpt_clkevt_time_stop(struct timer_of *to, u8 timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) writel(val & ~GPT_CTRL_ENABLE, timer_of_base(to) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) GPT_CTRL_REG(timer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static void mtk_gpt_clkevt_time_setup(struct timer_of *to,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned long delay, u8 timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) writel(delay, timer_of_base(to) + GPT_CMP_REG(timer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static void mtk_gpt_clkevt_time_start(struct timer_of *to,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) bool periodic, u8 timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Acknowledge interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) writel(GPT_IRQ_ACK(timer), timer_of_base(to) + GPT_IRQ_ACK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Clear 2 bit timer operation mode field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) val &= ~GPT_CTRL_OP(0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (periodic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) val |= GPT_CTRL_OP(GPT_CTRL_OP_REPEAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) val |= GPT_CTRL_OP(GPT_CTRL_OP_ONESHOT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) writel(val | GPT_CTRL_ENABLE | GPT_CTRL_CLEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) timer_of_base(to) + GPT_CTRL_REG(timer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int mtk_gpt_clkevt_shutdown(struct clock_event_device *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) mtk_gpt_clkevt_time_stop(to_timer_of(clk), TIMER_CLK_EVT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int mtk_gpt_clkevt_set_periodic(struct clock_event_device *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct timer_of *to = to_timer_of(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) mtk_gpt_clkevt_time_stop(to, TIMER_CLK_EVT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) mtk_gpt_clkevt_time_setup(to, to->of_clk.period, TIMER_CLK_EVT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) mtk_gpt_clkevt_time_start(to, true, TIMER_CLK_EVT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int mtk_gpt_clkevt_next_event(unsigned long event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct clock_event_device *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct timer_of *to = to_timer_of(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) mtk_gpt_clkevt_time_stop(to, TIMER_CLK_EVT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) mtk_gpt_clkevt_time_setup(to, event, TIMER_CLK_EVT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) mtk_gpt_clkevt_time_start(to, false, TIMER_CLK_EVT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static irqreturn_t mtk_gpt_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct clock_event_device *clkevt = (struct clock_event_device *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct timer_of *to = to_timer_of(clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Acknowledge timer0 irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) writel(GPT_IRQ_ACK(TIMER_CLK_EVT), timer_of_base(to) + GPT_IRQ_ACK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) clkevt->event_handler(clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) __init mtk_gpt_setup(struct timer_of *to, u8 timer, u8 option)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) writel(GPT_CTRL_CLEAR | GPT_CTRL_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) timer_of_base(to) + GPT_CTRL_REG(timer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) writel(GPT_CLK_SRC(GPT_CLK_SRC_SYS13M) | GPT_CLK_DIV1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) timer_of_base(to) + GPT_CLK_REG(timer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) writel(0x0, timer_of_base(to) + GPT_CMP_REG(timer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) writel(GPT_CTRL_OP(option) | GPT_CTRL_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) timer_of_base(to) + GPT_CTRL_REG(timer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static void mtk_gpt_enable_irq(struct timer_of *to, u8 timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) writel(0x0, timer_of_base(to) + GPT_IRQ_EN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* Acknowledge all spurious pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) writel(0x3f, timer_of_base(to) + GPT_IRQ_ACK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) val = readl(timer_of_base(to) + GPT_IRQ_EN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) writel(val | GPT_IRQ_ENABLE(timer),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) timer_of_base(to) + GPT_IRQ_EN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static struct timer_of to = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .clkevt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .name = "mtk-clkevt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .rating = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .cpumask = cpu_possible_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .of_irq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .flags = IRQF_TIMER | IRQF_IRQPOLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int __init mtk_syst_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) to.clkevt.features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_ONESHOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) to.clkevt.set_state_shutdown = mtk_syst_clkevt_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) to.clkevt.set_state_oneshot = mtk_syst_clkevt_oneshot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) to.clkevt.tick_resume = mtk_syst_clkevt_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) to.clkevt.set_next_event = mtk_syst_clkevt_next_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) to.of_irq.handler = mtk_syst_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ret = timer_of_init(node, &to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) TIMER_SYNC_TICKS, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int __init mtk_gpt_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) to.clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) to.clkevt.set_state_shutdown = mtk_gpt_clkevt_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) to.clkevt.set_state_periodic = mtk_gpt_clkevt_set_periodic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) to.clkevt.set_state_oneshot = mtk_gpt_clkevt_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) to.clkevt.tick_resume = mtk_gpt_clkevt_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) to.clkevt.set_next_event = mtk_gpt_clkevt_next_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) to.of_irq.handler = mtk_gpt_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ret = timer_of_init(node, &to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* Configure clock source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) mtk_gpt_setup(&to, TIMER_CLK_SRC, GPT_CTRL_OP_FREERUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) clocksource_mmio_init(timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) node->name, timer_of_rate(&to), 300, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) clocksource_mmio_readl_up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) gpt_sched_reg = timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) sched_clock_register(mtk_gpt_read_sched_clock, 32, timer_of_rate(&to));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* Configure clock event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) mtk_gpt_setup(&to, TIMER_CLK_EVT, GPT_CTRL_OP_REPEAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) TIMER_SYNC_TICKS, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) mtk_gpt_enable_irq(&to, TIMER_CLK_EVT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) TIMER_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_gpt_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) TIMER_OF_DECLARE(mtk_mt6765, "mediatek,mt6765-timer", mtk_syst_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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