^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Clocksource driver for NXP LPC32xx/18xx/43xx timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Based on:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * time-efm32 Copyright (C) 2013 Pengutronix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * mach-lpc32xx/timer.c Copyright (C) 2009 - 2010 NXP Semiconductors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define pr_fmt(fmt) "%s: " fmt, __func__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LPC32XX_TIMER_IR 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LPC32XX_TIMER_IR_MR0INT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define LPC32XX_TIMER_TCR 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define LPC32XX_TIMER_TCR_CEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LPC32XX_TIMER_TCR_CRST BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LPC32XX_TIMER_TC 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LPC32XX_TIMER_PR 0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LPC32XX_TIMER_MCR 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define LPC32XX_TIMER_MCR_MR0I BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define LPC32XX_TIMER_MCR_MR0R BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LPC32XX_TIMER_MCR_MR0S BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LPC32XX_TIMER_MR0 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define LPC32XX_TIMER_CTCR 0x070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct lpc32xx_clock_event_ddata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct clock_event_device evtdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 ticks_per_jiffy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Needed for the sched clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static void __iomem *clocksource_timer_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static u64 notrace lpc32xx_read_sched_clock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return readl(clocksource_timer_counter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static unsigned long lpc32xx_delay_timer_read(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return readl(clocksource_timer_counter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static struct delay_timer lpc32xx_delay_timer = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .read_current_timer = lpc32xx_delay_timer_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static int lpc32xx_clkevt_next_event(unsigned long delta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct clock_event_device *evtdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct lpc32xx_clock_event_ddata *ddata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) container_of(evtdev, struct lpc32xx_clock_event_ddata, evtdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * Place timer in reset and program the delta in the match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * channel 0 (MR0). When the timer counter matches the value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * in MR0 register the match will trigger an interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * After setup the timer is released from reset and enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) writel_relaxed(LPC32XX_TIMER_TCR_CRST, ddata->base + LPC32XX_TIMER_TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) writel_relaxed(delta, ddata->base + LPC32XX_TIMER_MR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) writel_relaxed(LPC32XX_TIMER_TCR_CEN, ddata->base + LPC32XX_TIMER_TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int lpc32xx_clkevt_shutdown(struct clock_event_device *evtdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct lpc32xx_clock_event_ddata *ddata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) container_of(evtdev, struct lpc32xx_clock_event_ddata, evtdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Disable the timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) writel_relaxed(0, ddata->base + LPC32XX_TIMER_TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static int lpc32xx_clkevt_oneshot(struct clock_event_device *evtdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct lpc32xx_clock_event_ddata *ddata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) container_of(evtdev, struct lpc32xx_clock_event_ddata, evtdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * When using oneshot, we must also disable the timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * to wait for the first call to set_next_event().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) writel_relaxed(0, ddata->base + LPC32XX_TIMER_TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Enable interrupt, reset on match and stop on match (MCR). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) writel_relaxed(LPC32XX_TIMER_MCR_MR0I | LPC32XX_TIMER_MCR_MR0R |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) LPC32XX_TIMER_MCR_MR0S, ddata->base + LPC32XX_TIMER_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static int lpc32xx_clkevt_periodic(struct clock_event_device *evtdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct lpc32xx_clock_event_ddata *ddata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) container_of(evtdev, struct lpc32xx_clock_event_ddata, evtdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Enable interrupt and reset on match. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) writel_relaxed(LPC32XX_TIMER_MCR_MR0I | LPC32XX_TIMER_MCR_MR0R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ddata->base + LPC32XX_TIMER_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * Place timer in reset and program the delta in the match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * channel 0 (MR0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) writel_relaxed(LPC32XX_TIMER_TCR_CRST, ddata->base + LPC32XX_TIMER_TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) writel_relaxed(ddata->ticks_per_jiffy, ddata->base + LPC32XX_TIMER_MR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) writel_relaxed(LPC32XX_TIMER_TCR_CEN, ddata->base + LPC32XX_TIMER_TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static irqreturn_t lpc32xx_clock_event_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct lpc32xx_clock_event_ddata *ddata = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Clear match on channel 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) writel_relaxed(LPC32XX_TIMER_IR_MR0INT, ddata->base + LPC32XX_TIMER_IR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ddata->evtdev.event_handler(&ddata->evtdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static struct lpc32xx_clock_event_ddata lpc32xx_clk_event_ddata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .evtdev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .name = "lpc3220 clockevent",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .features = CLOCK_EVT_FEAT_ONESHOT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) CLOCK_EVT_FEAT_PERIODIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .rating = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .set_next_event = lpc32xx_clkevt_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .set_state_shutdown = lpc32xx_clkevt_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .set_state_oneshot = lpc32xx_clkevt_oneshot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .set_state_periodic = lpc32xx_clkevt_periodic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int __init lpc32xx_clocksource_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) clk = of_clk_get_by_name(np, "timerclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) pr_err("clock get failed (%ld)\n", PTR_ERR(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) pr_err("clock enable failed (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) goto err_clk_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) pr_err("unable to map registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ret = -EADDRNOTAVAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) goto err_iomap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * Disable and reset timer then set it to free running timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * mode (CTCR) with no prescaler (PR) or match operations (MCR).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * After setup the timer is released from reset and enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) writel_relaxed(LPC32XX_TIMER_TCR_CRST, base + LPC32XX_TIMER_TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) writel_relaxed(0, base + LPC32XX_TIMER_PR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) writel_relaxed(0, base + LPC32XX_TIMER_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) writel_relaxed(0, base + LPC32XX_TIMER_CTCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) writel_relaxed(LPC32XX_TIMER_TCR_CEN, base + LPC32XX_TIMER_TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ret = clocksource_mmio_init(base + LPC32XX_TIMER_TC, "lpc3220 timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) rate, 300, 32, clocksource_mmio_readl_up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) pr_err("failed to init clocksource (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) goto err_clocksource_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) clocksource_timer_counter = base + LPC32XX_TIMER_TC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) lpc32xx_delay_timer.freq = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) register_current_timer_delay(&lpc32xx_delay_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) sched_clock_register(lpc32xx_read_sched_clock, 32, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) err_clocksource_init:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) err_iomap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) err_clk_enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static int __init lpc32xx_clockevent_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) clk = of_clk_get_by_name(np, "timerclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) pr_err("clock get failed (%ld)\n", PTR_ERR(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) pr_err("clock enable failed (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) goto err_clk_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) pr_err("unable to map registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ret = -EADDRNOTAVAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) goto err_iomap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) irq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (!irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) pr_err("get irq failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ret = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) goto err_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * Disable timer and clear any pending interrupt (IR) on match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * channel 0 (MR0). Clear the prescaler as it's not used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) writel_relaxed(0, base + LPC32XX_TIMER_TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) writel_relaxed(0, base + LPC32XX_TIMER_PR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) writel_relaxed(0, base + LPC32XX_TIMER_CTCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) writel_relaxed(LPC32XX_TIMER_IR_MR0INT, base + LPC32XX_TIMER_IR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) lpc32xx_clk_event_ddata.base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) lpc32xx_clk_event_ddata.ticks_per_jiffy = DIV_ROUND_CLOSEST(rate, HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) clockevents_config_and_register(&lpc32xx_clk_event_ddata.evtdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) rate, 1, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ret = request_irq(irq, lpc32xx_clock_event_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) IRQF_TIMER | IRQF_IRQPOLL, "lpc3220 clockevent",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) &lpc32xx_clk_event_ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) pr_err("request irq failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) goto err_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) err_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) err_iomap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) err_clk_enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * This function asserts that we have exactly one clocksource and one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * clock_event_device in the end.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int __init lpc32xx_timer_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int has_clocksource, has_clockevent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (!has_clocksource) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) ret = lpc32xx_clocksource_init(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) has_clocksource = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (!has_clockevent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ret = lpc32xx_clockevent_init(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) has_clockevent = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) TIMER_OF_DECLARE(lpc32xx_timer, "nxp,lpc3220-timer", lpc32xx_timer_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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