Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Keystone broadcast clock-event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2013 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Author: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define TIMER_NAME			"timer-keystone"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) /* Timer register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define TIM12				0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define TIM34				0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define PRD12				0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define PRD34				0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define TCR				0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define TGCR				0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define INTCTLSTAT			0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* Timer register bitfields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define TCR_ENAMODE_MASK		0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define TCR_ENAMODE_ONESHOT_MASK	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define TCR_ENAMODE_PERIODIC_MASK	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define TGCR_TIM_UNRESET_MASK		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define INTCTLSTAT_ENINT_MASK		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * struct keystone_timer: holds timer's data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * @base: timer memory base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * @hz_period: cycles per HZ period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * @event_dev: event device based on timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) static struct keystone_timer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	unsigned long hz_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	struct clock_event_device event_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) } timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static inline u32 keystone_timer_readl(unsigned long rg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	return readl_relaxed(timer.base + rg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static inline void keystone_timer_writel(u32 val, unsigned long rg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	writel_relaxed(val, timer.base + rg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  * keystone_timer_barrier: write memory barrier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  * use explicit barrier to avoid using readl/writel non relaxed function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  * variants, because in our case non relaxed variants hide the true places
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  * where barrier is needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static inline void keystone_timer_barrier(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	__iowmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  * keystone_timer_config: configures timer to work in oneshot/periodic modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  * @ mask: mask of the mode to configure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  * @ period: cycles number to configure for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static int keystone_timer_config(u64 period, int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	u32 tcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	u32 off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	tcr = keystone_timer_readl(TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	off = tcr & ~(TCR_ENAMODE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	/* set enable mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	tcr |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	/* disable timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	keystone_timer_writel(off, TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	/* here we have to be sure the timer has been disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	keystone_timer_barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	/* reset counter to zero, set new period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	keystone_timer_writel(0, TIM12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	keystone_timer_writel(0, TIM34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	keystone_timer_writel(period & 0xffffffff, PRD12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	keystone_timer_writel(period >> 32, PRD34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	 * enable timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	 * here we have to be sure that CNTLO, CNTHI, PRDLO, PRDHI registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	 * have been written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	keystone_timer_barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	keystone_timer_writel(tcr, TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static void keystone_timer_disable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	u32 tcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	tcr = keystone_timer_readl(TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	/* disable timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	tcr &= ~(TCR_ENAMODE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	keystone_timer_writel(tcr, TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static irqreturn_t keystone_timer_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	struct clock_event_device *evt = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	evt->event_handler(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int keystone_set_next_event(unsigned long cycles,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 				  struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	return keystone_timer_config(cycles, TCR_ENAMODE_ONESHOT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int keystone_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	keystone_timer_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int keystone_set_periodic(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	keystone_timer_config(timer.hz_period, TCR_ENAMODE_PERIODIC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int __init keystone_timer_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	struct clock_event_device *event_dev = &timer.event_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	int irq, error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	irq  = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	if (!irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		pr_err("%s: failed to map interrupts\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	timer.base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	if (!timer.base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		pr_err("%s: failed to map registers\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	clk = of_clk_get(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		pr_err("%s: failed to get clock\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		iounmap(timer.base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	error = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		pr_err("%s: failed to enable clock\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	/* disable, use internal clock source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	keystone_timer_writel(0, TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	/* here we have to be sure the timer has been disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	keystone_timer_barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	/* reset timer as 64-bit, no pre-scaler, plus features are disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	keystone_timer_writel(0, TGCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	/* unreset timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	keystone_timer_writel(TGCR_TIM_UNRESET_MASK, TGCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	/* init counter to zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	keystone_timer_writel(0, TIM12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	keystone_timer_writel(0, TIM34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	timer.hz_period = DIV_ROUND_UP(rate, HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	/* enable timer interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	keystone_timer_writel(INTCTLSTAT_ENINT_MASK, INTCTLSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	error = request_irq(irq, keystone_timer_interrupt, IRQF_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 			    TIMER_NAME, event_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		pr_err("%s: failed to setup irq\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	/* setup clockevent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	event_dev->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	event_dev->set_next_event = keystone_set_next_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	event_dev->set_state_shutdown = keystone_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	event_dev->set_state_periodic = keystone_set_periodic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	event_dev->set_state_oneshot = keystone_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	event_dev->cpumask = cpu_possible_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	event_dev->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	event_dev->name = TIMER_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	event_dev->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	clockevents_config_and_register(event_dev, rate, 1, ULONG_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	pr_info("keystone timer clock @%lu Hz\n", rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	iounmap(timer.base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) TIMER_OF_DECLARE(keystone_timer, "ti,keystone-timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 			   keystone_timer_init);