^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * IXP4 timer driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2019 Linus Walleij <linus.walleij@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Based on arch/arm/mach-ixp4xx/common.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2002 (C) Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright 2003-2004 (C) MontaVista, Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) Deepak Saxena <dsaxena@plexity.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Goes away with OF conversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_data/timer-ixp4xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Constants to make it easy to access Timer Control/Status registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IXP4XX_OSTS_OFFSET 0x00 /* Continuous Timestamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IXP4XX_OST1_OFFSET 0x04 /* Timer 1 Timestamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IXP4XX_OSRT1_OFFSET 0x08 /* Timer 1 Reload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IXP4XX_OST2_OFFSET 0x0C /* Timer 2 Timestamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IXP4XX_OSRT2_OFFSET 0x10 /* Timer 2 Reload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IXP4XX_OSWT_OFFSET 0x14 /* Watchdog Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IXP4XX_OSWE_OFFSET 0x18 /* Watchdog Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IXP4XX_OSWK_OFFSET 0x1C /* Watchdog Key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IXP4XX_OSST_OFFSET 0x20 /* Timer Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Timer register values and bit definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IXP4XX_OST_ENABLE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IXP4XX_OST_ONE_SHOT 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* Low order bits of reload value ignored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IXP4XX_OST_RELOAD_MASK 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IXP4XX_OST_DISABLED 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IXP4XX_OSST_TIMER_1_PEND 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IXP4XX_OSST_TIMER_2_PEND 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IXP4XX_OSST_TIMER_TS_PEND 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IXP4XX_OSST_TIMER_WDOG_PEND 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IXP4XX_OSST_TIMER_WARM_RESET 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IXP4XX_WDT_KEY 0x0000482E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IXP4XX_WDT_RESET_ENABLE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IXP4XX_WDT_IRQ_ENABLE 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IXP4XX_WDT_COUNT_ENABLE 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct ixp4xx_timer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned int tick_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 latch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct clock_event_device clkevt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #ifdef CONFIG_ARM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct delay_timer delay_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * A local singleton used by sched_clock and delay timer reads, which are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * fast and stateless
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static struct ixp4xx_timer *local_ixp4xx_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static inline struct ixp4xx_timer *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) to_ixp4xx_timer(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return container_of(evt, struct ixp4xx_timer, clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static unsigned long ixp4xx_read_timer(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return __raw_readl(local_ixp4xx_timer->base + IXP4XX_OSTS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static u64 notrace ixp4xx_read_sched_clock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return ixp4xx_read_timer();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static u64 ixp4xx_clocksource_read(struct clocksource *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return ixp4xx_read_timer();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct ixp4xx_timer *tmr = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct clock_event_device *evt = &tmr->clkevt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Clear Pending Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) __raw_writel(IXP4XX_OSST_TIMER_1_PEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) tmr->base + IXP4XX_OSST_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) evt->event_handler(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int ixp4xx_set_next_event(unsigned long cycles,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Keep enable/oneshot bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) val &= IXP4XX_OST_RELOAD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) __raw_writel((cycles & ~IXP4XX_OST_RELOAD_MASK) | val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) tmr->base + IXP4XX_OSRT1_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int ixp4xx_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) val &= ~IXP4XX_OST_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) __raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int ixp4xx_set_oneshot(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) __raw_writel(IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) tmr->base + IXP4XX_OSRT1_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int ixp4xx_set_periodic(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) val = tmr->latch & ~IXP4XX_OST_RELOAD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) val |= IXP4XX_OST_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) __raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int ixp4xx_resume(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) val |= IXP4XX_OST_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) __raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * IXP4xx timer tick
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * We use OS timer1 on the CPU for the timer tick and the timestamp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * counter as a source of real clock ticks to account for missed jiffies.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static __init int ixp4xx_timer_register(void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int timer_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned int timer_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct ixp4xx_timer *tmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) tmr = kzalloc(sizeof(*tmr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (!tmr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) tmr->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) tmr->tick_rate = timer_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * The timer register doesn't allow to specify the two least
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * significant bits of the timeout value and assumes them being zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * So make sure the latch is the best value with the two least
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * significant bits unset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) tmr->latch = DIV_ROUND_CLOSEST(timer_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) (IXP4XX_OST_RELOAD_MASK + 1) * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * (IXP4XX_OST_RELOAD_MASK + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) local_ixp4xx_timer = tmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* Reset/disable counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) __raw_writel(0, tmr->base + IXP4XX_OSRT1_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* Clear any pending interrupt on timer 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) __raw_writel(IXP4XX_OSST_TIMER_1_PEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) tmr->base + IXP4XX_OSST_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* Reset time-stamp counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) __raw_writel(0, tmr->base + IXP4XX_OSTS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) clocksource_mmio_init(NULL, "OSTS", timer_freq, 200, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ixp4xx_clocksource_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) tmr->clkevt.name = "ixp4xx timer1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) tmr->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) tmr->clkevt.rating = 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) tmr->clkevt.set_state_shutdown = ixp4xx_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) tmr->clkevt.set_state_periodic = ixp4xx_set_periodic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) tmr->clkevt.set_state_oneshot = ixp4xx_set_oneshot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) tmr->clkevt.tick_resume = ixp4xx_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) tmr->clkevt.set_next_event = ixp4xx_set_next_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) tmr->clkevt.cpumask = cpumask_of(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) tmr->clkevt.irq = timer_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ret = request_irq(timer_irq, ixp4xx_timer_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) IRQF_TIMER, "IXP4XX-TIMER1", tmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) pr_crit("no timer IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) clockevents_config_and_register(&tmr->clkevt, timer_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 0xf, 0xfffffffe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) sched_clock_register(ixp4xx_read_sched_clock, 32, timer_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #ifdef CONFIG_ARM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Also use this timer for delays */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) tmr->delay_timer.read_current_timer = ixp4xx_read_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) tmr->delay_timer.freq = timer_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) register_current_timer_delay(&tmr->delay_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * ixp4xx_timer_setup() - Timer setup function to be called from boardfiles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * @timerbase: physical base of timer block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * @timer_irq: Linux IRQ number for the timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * @timer_freq: Fixed frequency of the timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) void __init ixp4xx_timer_setup(resource_size_t timerbase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int timer_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) unsigned int timer_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) base = ioremap(timerbase, 0x100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) pr_crit("IXP4xx: can't remap timer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ixp4xx_timer_register(base, timer_irq, timer_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) EXPORT_SYMBOL_GPL(ixp4xx_timer_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static __init int ixp4xx_of_timer_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) pr_crit("IXP4xx: can't remap timer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) irq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) pr_err("Can't parse IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) goto out_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* TODO: get some fixed clocks into the device tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ret = ixp4xx_timer_register(base, irq, 66666000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) goto out_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) out_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) TIMER_OF_DECLARE(ixp4xx, "intel,ixp4xx-timer", ixp4xx_of_timer_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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