Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Integrator/AP timer driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2000-2003 Deep Blue Solutions Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2014, Linaro Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "timer-sp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) static void __iomem * sched_clk_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) static u64 notrace integrator_read_sched_clock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	return -readl(sched_clk_base + TIMER_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static int __init integrator_clocksource_init(unsigned long inrate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 					      void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	unsigned long rate = inrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	if (rate >= 1500000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 		rate /= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		ctrl |= TIMER_CTRL_DIV16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	writel(0xffff, base + TIMER_LOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	writel(ctrl, base + TIMER_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	ret = clocksource_mmio_init(base + TIMER_VALUE, "timer2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 				    rate, 200, 16, clocksource_mmio_readl_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	sched_clk_base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	sched_clock_register(integrator_read_sched_clock, 16, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static unsigned long timer_reload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static void __iomem * clkevt_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  * IRQ handler for the timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	struct clock_event_device *evt = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	/* clear the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	writel(1, clkevt_base + TIMER_INTCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	evt->event_handler(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) static int clkevt_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	/* Disable timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	writel(ctrl, clkevt_base + TIMER_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static int clkevt_set_oneshot(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	u32 ctrl = readl(clkevt_base + TIMER_CTRL) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		   ~(TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	/* Leave the timer disabled, .set_next_event will enable it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	writel(ctrl, clkevt_base + TIMER_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static int clkevt_set_periodic(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	/* Disable timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	writel(ctrl, clkevt_base + TIMER_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	/* Enable the timer and start the periodic tick */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	writel(timer_reload, clkevt_base + TIMER_LOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	writel(ctrl, clkevt_base + TIMER_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	writel(next, clkevt_base + TIMER_LOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static struct clock_event_device integrator_clockevent = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	.name			= "timer1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	.features		= CLOCK_EVT_FEAT_PERIODIC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 				  CLOCK_EVT_FEAT_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	.set_state_shutdown	= clkevt_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	.set_state_periodic	= clkevt_set_periodic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	.set_state_oneshot	= clkevt_set_oneshot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	.tick_resume		= clkevt_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	.set_next_event		= clkevt_set_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	.rating			= 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int integrator_clockevent_init(unsigned long inrate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 				      void __iomem *base, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	unsigned long rate = inrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	unsigned int ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	clkevt_base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	/* Calculate and program a divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	if (rate > 0x100000 * HZ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		rate /= 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		ctrl |= TIMER_CTRL_DIV256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	} else if (rate > 0x10000 * HZ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		rate /= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		ctrl |= TIMER_CTRL_DIV16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	timer_reload = rate / HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	writel(ctrl, clkevt_base + TIMER_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	ret = request_irq(irq, integrator_timer_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 			  IRQF_TIMER | IRQF_IRQPOLL, "timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			  &integrator_clockevent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	clockevents_config_and_register(&integrator_clockevent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 					rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 					1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 					0xffffU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int __init integrator_ap_timer_init_of(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	const char *path;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	struct device_node *alias_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	base = of_io_request_and_map(node, 0, "integrator-timer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	clk = of_clk_get(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		pr_err("No clock for %pOFn\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	writel(0, base + TIMER_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	err = of_property_read_string(of_aliases,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 				"arm,timer-primary", &path);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		pr_warn("Failed to read property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	alias_node = of_find_node_by_path(path);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	 * The pointer is used as an identifier not as a pointer, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	 * can drop the refcount on the of__node immediately after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	 * getting it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	of_node_put(alias_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	if (node == alias_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		/* The primary timer lacks IRQ, use as clocksource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		return integrator_clocksource_init(rate, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	err = of_property_read_string(of_aliases,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 				"arm,timer-secondary", &path);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		pr_warn("Failed to read property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	alias_node = of_find_node_by_path(path);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	of_node_put(alias_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	if (node == alias_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		/* The secondary timer will drive the clock event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		irq = irq_of_parse_and_map(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		return integrator_clockevent_init(rate, base, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	pr_info("Timer @%p unused\n", base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) TIMER_OF_DECLARE(integrator_ap_timer, "arm,integrator-timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		       integrator_ap_timer_init_of);