Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // Copyright 2016 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) // Copyright 2017 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include "timer-of.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define TPM_PARAM			0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define TPM_PARAM_WIDTH_SHIFT		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define TPM_PARAM_WIDTH_MASK		(0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define TPM_SC				0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define TPM_SC_CMOD_INC_PER_CNT		(0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define TPM_SC_CMOD_DIV_DEFAULT		0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define TPM_SC_CMOD_DIV_MAX		0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define TPM_SC_TOF_MASK			(0x1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define TPM_CNT				0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define TPM_MOD				0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define TPM_STATUS			0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define TPM_STATUS_CH0F			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define TPM_C0SC			0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define TPM_C0SC_CHIE			BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define TPM_C0SC_MODE_SHIFT		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define TPM_C0SC_MODE_MASK		0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define TPM_C0SC_MODE_SW_COMPARE	0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define TPM_C0SC_CHF_MASK		(0x1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define TPM_C0V				0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) static int counter_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static void __iomem *timer_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) static inline void tpm_timer_disable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	/* channel disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	val = readl(timer_base + TPM_C0SC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	val &= ~(TPM_C0SC_MODE_MASK | TPM_C0SC_CHIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	writel(val, timer_base + TPM_C0SC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static inline void tpm_timer_enable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	/* channel enabled in sw compare mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	val = readl(timer_base + TPM_C0SC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	val |= (TPM_C0SC_MODE_SW_COMPARE << TPM_C0SC_MODE_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	       TPM_C0SC_CHIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	writel(val, timer_base + TPM_C0SC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static inline void tpm_irq_acknowledge(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	writel(TPM_STATUS_CH0F, timer_base + TPM_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static inline unsigned long tpm_read_counter(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	return readl(timer_base + TPM_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #if defined(CONFIG_ARM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) static struct delay_timer tpm_delay_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static unsigned long tpm_read_current_timer(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	return tpm_read_counter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static u64 notrace tpm_read_sched_clock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	return tpm_read_counter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static int tpm_set_next_event(unsigned long delta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 				struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	unsigned long next, now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	next = tpm_read_counter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	next += delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	writel(next, timer_base + TPM_C0V);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	now = tpm_read_counter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	 * NOTE: We observed in a very small probability, the bus fabric
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	 * contention between GPU and A7 may results a few cycles delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	 * of writing CNT registers which may cause the min_delta event got
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	 * missed, so we need add a ETIME check here in case it happened.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	return (int)(next - now) <= 0 ? -ETIME : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int tpm_set_state_oneshot(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	tpm_timer_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int tpm_set_state_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	tpm_timer_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static irqreturn_t tpm_timer_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	struct clock_event_device *evt = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	tpm_irq_acknowledge();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	evt->event_handler(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static struct timer_of to_tpm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	.flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	.clkevt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		.name			= "i.MX7ULP TPM Timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		.rating			= 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		.features		= CLOCK_EVT_FEAT_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		.set_state_shutdown	= tpm_set_state_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		.set_state_oneshot	= tpm_set_state_oneshot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		.set_next_event		= tpm_set_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		.cpumask		= cpu_possible_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	.of_irq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		.handler		= tpm_timer_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		.flags			= IRQF_TIMER | IRQF_IRQPOLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	.of_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		.name = "per",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int __init tpm_clocksource_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #if defined(CONFIG_ARM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	tpm_delay_timer.read_current_timer = &tpm_read_current_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	tpm_delay_timer.freq = timer_of_rate(&to_tpm) >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	register_current_timer_delay(&tpm_delay_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	sched_clock_register(tpm_read_sched_clock, counter_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 			     timer_of_rate(&to_tpm) >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	return clocksource_mmio_init(timer_base + TPM_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 				     "imx-tpm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 				     timer_of_rate(&to_tpm) >> 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 				     to_tpm.clkevt.rating,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 				     counter_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 				     clocksource_mmio_readl_up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static void __init tpm_clockevent_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	clockevents_config_and_register(&to_tpm.clkevt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 					timer_of_rate(&to_tpm) >> 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 					300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 					GENMASK(counter_width - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 					1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int __init tpm_timer_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	struct clk *ipg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	ipg = of_clk_get_by_name(np, "ipg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	if (IS_ERR(ipg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		pr_err("tpm: failed to get ipg clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	/* enable clk before accessing registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	ret = clk_prepare_enable(ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		pr_err("tpm: ipg clock enable failed (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		clk_put(ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	ret = timer_of_init(np, &to_tpm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	timer_base = timer_of_base(&to_tpm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	counter_width = (readl(timer_base + TPM_PARAM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		& TPM_PARAM_WIDTH_MASK) >> TPM_PARAM_WIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	/* use rating 200 for 32-bit counter and 150 for 16-bit counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	to_tpm.clkevt.rating = counter_width == 0x20 ? 200 : 150;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	 * Initialize tpm module to a known state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	 * 1) Counter disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	 * 2) TPM counter operates in up counting mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	 * 3) Timer Overflow Interrupt disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	 * 4) Channel0 disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	 * 5) DMA transfers disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	/* make sure counter is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	writel(0, timer_base + TPM_SC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	/* TOF is W1C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	writel(TPM_SC_TOF_MASK, timer_base + TPM_SC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	writel(0, timer_base + TPM_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	/* CHF is W1C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	writel(TPM_C0SC_CHF_MASK, timer_base + TPM_C0SC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	 * increase per cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	 * div 8 for 32-bit counter and div 128 for 16-bit counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	writel(TPM_SC_CMOD_INC_PER_CNT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		(counter_width == 0x20 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		TPM_SC_CMOD_DIV_DEFAULT : TPM_SC_CMOD_DIV_MAX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		timer_base + TPM_SC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	/* set MOD register to maximum for free running mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	writel(GENMASK(counter_width - 1, 0), timer_base + TPM_MOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	tpm_clockevent_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	return tpm_clocksource_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) TIMER_OF_DECLARE(imx7ulp, "fsl,imx7ulp-tpm", tpm_timer_init);