^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (C) 2000-2001 Deep Blue Solutions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // Copyright (C) 2002 Shane Nay (shane@minirl.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <soc/imx/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * There are 4 versions of the timer hardware on Freescale MXC hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * - MX1/MXL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * - MX21, MX27.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * - MX25, MX31, MX35, MX37, MX51, MX6Q(rev1.0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * - MX6DL, MX6SX, MX6Q(rev1.1+)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* defines common for all i.MX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MXC_TCTL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MXC_TCTL_TEN (1 << 0) /* Enable module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MXC_TPRER 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* MX1, MX21, MX27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MX1_2_TCTL_CLK_PCLK1 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MX1_2_TCTL_IRQEN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MX1_2_TCTL_FRR (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MX1_2_TCMP 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MX1_2_TCN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MX1_2_TSTAT 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* MX21, MX27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MX2_TSTAT_CAPT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MX2_TSTAT_COMP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* MX31, MX35, MX25, MX5, MX6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define V2_TCTL_CLK_IPG (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define V2_TCTL_CLK_PER (2 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define V2_TCTL_CLK_OSC_DIV8 (5 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define V2_TCTL_FRR (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define V2_TCTL_24MEN (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define V2_TPRER_PRE24M 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define V2_IR 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define V2_TSTAT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define V2_TSTAT_OF1 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define V2_TCN 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define V2_TCMP 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define V2_TIMER_RATE_OSC_DIV8 3000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct imx_timer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) enum imx_gpt_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct clk *clk_per;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct clk *clk_ipg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) const struct imx_gpt_data *gpt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct clock_event_device ced;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct imx_gpt_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int reg_tstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int reg_tcn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int reg_tcmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) void (*gpt_setup_tctl)(struct imx_timer *imxtm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) void (*gpt_irq_enable)(struct imx_timer *imxtm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) void (*gpt_irq_disable)(struct imx_timer *imxtm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) void (*gpt_irq_acknowledge)(struct imx_timer *imxtm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int (*set_next_event)(unsigned long evt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct clock_event_device *ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static inline struct imx_timer *to_imx_timer(struct clock_event_device *ced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return container_of(ced, struct imx_timer, ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static void imx1_gpt_irq_disable(struct imx_timer *imxtm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) tmp = readl_relaxed(imxtm->base + MXC_TCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define imx21_gpt_irq_disable imx1_gpt_irq_disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static void imx31_gpt_irq_disable(struct imx_timer *imxtm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) writel_relaxed(0, imxtm->base + V2_IR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define imx6dl_gpt_irq_disable imx31_gpt_irq_disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static void imx1_gpt_irq_enable(struct imx_timer *imxtm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) tmp = readl_relaxed(imxtm->base + MXC_TCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) writel_relaxed(tmp | MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define imx21_gpt_irq_enable imx1_gpt_irq_enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static void imx31_gpt_irq_enable(struct imx_timer *imxtm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) writel_relaxed(1<<0, imxtm->base + V2_IR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define imx6dl_gpt_irq_enable imx31_gpt_irq_enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static void imx1_gpt_irq_acknowledge(struct imx_timer *imxtm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) writel_relaxed(0, imxtm->base + MX1_2_TSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static void imx21_gpt_irq_acknowledge(struct imx_timer *imxtm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) writel_relaxed(MX2_TSTAT_CAPT | MX2_TSTAT_COMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) imxtm->base + MX1_2_TSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static void imx31_gpt_irq_acknowledge(struct imx_timer *imxtm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) writel_relaxed(V2_TSTAT_OF1, imxtm->base + V2_TSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define imx6dl_gpt_irq_acknowledge imx31_gpt_irq_acknowledge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static void __iomem *sched_clock_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static u64 notrace mxc_read_sched_clock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return sched_clock_reg ? readl_relaxed(sched_clock_reg) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #if defined(CONFIG_ARM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static struct delay_timer imx_delay_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static unsigned long imx_read_current_timer(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return readl_relaxed(sched_clock_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int __init mxc_clocksource_init(struct imx_timer *imxtm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned int c = clk_get_rate(imxtm->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) void __iomem *reg = imxtm->base + imxtm->gpt->reg_tcn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #if defined(CONFIG_ARM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) imx_delay_timer.read_current_timer = &imx_read_current_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) imx_delay_timer.freq = c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) register_current_timer_delay(&imx_delay_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) sched_clock_reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) sched_clock_register(mxc_read_sched_clock, 32, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) clocksource_mmio_readl_up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* clock event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int mx1_2_set_next_event(unsigned long evt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct clock_event_device *ced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct imx_timer *imxtm = to_imx_timer(ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) unsigned long tcmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) tcmp = readl_relaxed(imxtm->base + MX1_2_TCN) + evt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) writel_relaxed(tcmp, imxtm->base + MX1_2_TCMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return (int)(tcmp - readl_relaxed(imxtm->base + MX1_2_TCN)) < 0 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) -ETIME : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int v2_set_next_event(unsigned long evt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct clock_event_device *ced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct imx_timer *imxtm = to_imx_timer(ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned long tcmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) tcmp = readl_relaxed(imxtm->base + V2_TCN) + evt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) writel_relaxed(tcmp, imxtm->base + V2_TCMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return evt < 0x7fffffff &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) (int)(tcmp - readl_relaxed(imxtm->base + V2_TCN)) < 0 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) -ETIME : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static int mxc_shutdown(struct clock_event_device *ced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct imx_timer *imxtm = to_imx_timer(ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u32 tcn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Disable interrupt in GPT module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) imxtm->gpt->gpt_irq_disable(imxtm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* Set event time into far-far future */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Clear pending interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) imxtm->gpt->gpt_irq_acknowledge(imxtm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) printk(KERN_INFO "%s: changing mode\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #endif /* DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int mxc_set_oneshot(struct clock_event_device *ced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct imx_timer *imxtm = to_imx_timer(ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* Disable interrupt in GPT module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) imxtm->gpt->gpt_irq_disable(imxtm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (!clockevent_state_oneshot(ced)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u32 tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* Set event time into far-far future */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* Clear pending interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) imxtm->gpt->gpt_irq_acknowledge(imxtm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) printk(KERN_INFO "%s: changing mode\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #endif /* DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * Do not put overhead of interrupt enable/disable into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * mxc_set_next_event(), the core has about 4 minutes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * to call mxc_set_next_event() or shutdown clock after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * mode switching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) imxtm->gpt->gpt_irq_enable(imxtm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * IRQ handler for the timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct clock_event_device *ced = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct imx_timer *imxtm = to_imx_timer(ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) uint32_t tstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) tstat = readl_relaxed(imxtm->base + imxtm->gpt->reg_tstat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) imxtm->gpt->gpt_irq_acknowledge(imxtm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ced->event_handler(ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static int __init mxc_clockevent_init(struct imx_timer *imxtm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct clock_event_device *ced = &imxtm->ced;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) ced->name = "mxc_timer1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) ced->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_DYNIRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ced->set_state_shutdown = mxc_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ced->set_state_oneshot = mxc_set_oneshot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ced->tick_resume = mxc_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ced->set_next_event = imxtm->gpt->set_next_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ced->rating = 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ced->cpumask = cpumask_of(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ced->irq = imxtm->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) clockevents_config_and_register(ced, clk_get_rate(imxtm->clk_per),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 0xff, 0xfffffffe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return request_irq(imxtm->irq, mxc_timer_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) IRQF_TIMER | IRQF_IRQPOLL, "i.MX Timer Tick", ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static void imx1_gpt_setup_tctl(struct imx_timer *imxtm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u32 tctl_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define imx21_gpt_setup_tctl imx1_gpt_setup_tctl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static void imx31_gpt_setup_tctl(struct imx_timer *imxtm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u32 tctl_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) tctl_val |= V2_TCTL_CLK_OSC_DIV8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) tctl_val |= V2_TCTL_CLK_PER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static void imx6dl_gpt_setup_tctl(struct imx_timer *imxtm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u32 tctl_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) tctl_val |= V2_TCTL_CLK_OSC_DIV8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* 24 / 8 = 3 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) writel_relaxed(7 << V2_TPRER_PRE24M, imxtm->base + MXC_TPRER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) tctl_val |= V2_TCTL_24MEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) tctl_val |= V2_TCTL_CLK_PER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static const struct imx_gpt_data imx1_gpt_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .reg_tstat = MX1_2_TSTAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .reg_tcn = MX1_2_TCN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .reg_tcmp = MX1_2_TCMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .gpt_irq_enable = imx1_gpt_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .gpt_irq_disable = imx1_gpt_irq_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .gpt_irq_acknowledge = imx1_gpt_irq_acknowledge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .gpt_setup_tctl = imx1_gpt_setup_tctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .set_next_event = mx1_2_set_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static const struct imx_gpt_data imx21_gpt_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .reg_tstat = MX1_2_TSTAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .reg_tcn = MX1_2_TCN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .reg_tcmp = MX1_2_TCMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .gpt_irq_enable = imx21_gpt_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .gpt_irq_disable = imx21_gpt_irq_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .gpt_irq_acknowledge = imx21_gpt_irq_acknowledge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .gpt_setup_tctl = imx21_gpt_setup_tctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .set_next_event = mx1_2_set_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static const struct imx_gpt_data imx31_gpt_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .reg_tstat = V2_TSTAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .reg_tcn = V2_TCN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .reg_tcmp = V2_TCMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .gpt_irq_enable = imx31_gpt_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .gpt_irq_disable = imx31_gpt_irq_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .gpt_irq_acknowledge = imx31_gpt_irq_acknowledge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .gpt_setup_tctl = imx31_gpt_setup_tctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .set_next_event = v2_set_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static const struct imx_gpt_data imx6dl_gpt_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .reg_tstat = V2_TSTAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .reg_tcn = V2_TCN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .reg_tcmp = V2_TCMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .gpt_irq_enable = imx6dl_gpt_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .gpt_irq_disable = imx6dl_gpt_irq_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .gpt_irq_acknowledge = imx6dl_gpt_irq_acknowledge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .gpt_setup_tctl = imx6dl_gpt_setup_tctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .set_next_event = v2_set_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static int __init _mxc_timer_init(struct imx_timer *imxtm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) switch (imxtm->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) case GPT_TYPE_IMX1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) imxtm->gpt = &imx1_gpt_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) case GPT_TYPE_IMX21:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) imxtm->gpt = &imx21_gpt_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) case GPT_TYPE_IMX31:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) imxtm->gpt = &imx31_gpt_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) case GPT_TYPE_IMX6DL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) imxtm->gpt = &imx6dl_gpt_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (IS_ERR(imxtm->clk_per)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) pr_err("i.MX timer: unable to get clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return PTR_ERR(imxtm->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (!IS_ERR(imxtm->clk_ipg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) clk_prepare_enable(imxtm->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) clk_prepare_enable(imxtm->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * Initialise to a known state (all timers off, and timing reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) writel_relaxed(0, imxtm->base + MXC_TCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) writel_relaxed(0, imxtm->base + MXC_TPRER); /* see datasheet note */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) imxtm->gpt->gpt_setup_tctl(imxtm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* init and register the timer to the framework */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ret = mxc_clocksource_init(imxtm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return mxc_clockevent_init(imxtm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) void __init mxc_timer_init(unsigned long pbase, int irq, enum imx_gpt_type type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct imx_timer *imxtm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) BUG_ON(!imxtm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) imxtm->clk_per = clk_get_sys("imx-gpt.0", "per");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) imxtm->clk_ipg = clk_get_sys("imx-gpt.0", "ipg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) imxtm->base = ioremap(pbase, SZ_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) BUG_ON(!imxtm->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) imxtm->type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) imxtm->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) _mxc_timer_init(imxtm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static int __init mxc_timer_init_dt(struct device_node *np, enum imx_gpt_type type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct imx_timer *imxtm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static int initialized;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* Support one instance only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (initialized)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (!imxtm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) imxtm->base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (!imxtm->base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) imxtm->irq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (imxtm->irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) imxtm->clk_ipg = of_clk_get_by_name(np, "ipg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* Try osc_per first, and fall back to per otherwise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) imxtm->clk_per = of_clk_get_by_name(np, "osc_per");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (IS_ERR(imxtm->clk_per))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) imxtm->clk_per = of_clk_get_by_name(np, "per");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) imxtm->type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ret = _mxc_timer_init(imxtm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) initialized = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static int __init imx1_timer_init_dt(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return mxc_timer_init_dt(np, GPT_TYPE_IMX1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static int __init imx21_timer_init_dt(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return mxc_timer_init_dt(np, GPT_TYPE_IMX21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static int __init imx31_timer_init_dt(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) enum imx_gpt_type type = GPT_TYPE_IMX31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * We were using the same compatible string for i.MX6Q/D and i.MX6DL/S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * GPT device, while they actually have different programming model.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * This is a workaround to keep the existing i.MX6DL/S DTBs continue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * working with the new kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (of_machine_is_compatible("fsl,imx6dl"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) type = GPT_TYPE_IMX6DL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return mxc_timer_init_dt(np, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static int __init imx6dl_timer_init_dt(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return mxc_timer_init_dt(np, GPT_TYPE_IMX6DL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) TIMER_OF_DECLARE(imx1_timer, "fsl,imx1-gpt", imx1_timer_init_dt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) TIMER_OF_DECLARE(imx21_timer, "fsl,imx21-gpt", imx21_timer_init_dt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) TIMER_OF_DECLARE(imx27_timer, "fsl,imx27-gpt", imx21_timer_init_dt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) TIMER_OF_DECLARE(imx31_timer, "fsl,imx31-gpt", imx31_timer_init_dt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) TIMER_OF_DECLARE(imx25_timer, "fsl,imx25-gpt", imx31_timer_init_dt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) TIMER_OF_DECLARE(imx50_timer, "fsl,imx50-gpt", imx31_timer_init_dt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) TIMER_OF_DECLARE(imx51_timer, "fsl,imx51-gpt", imx31_timer_init_dt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) TIMER_OF_DECLARE(imx53_timer, "fsl,imx53-gpt", imx31_timer_init_dt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) TIMER_OF_DECLARE(imx6q_timer, "fsl,imx6q-gpt", imx31_timer_init_dt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) TIMER_OF_DECLARE(imx6dl_timer, "fsl,imx6dl-gpt", imx6dl_timer_init_dt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) TIMER_OF_DECLARE(imx6sl_timer, "fsl,imx6sl-gpt", imx6dl_timer_init_dt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) TIMER_OF_DECLARE(imx6sx_timer, "fsl,imx6sx-gpt", imx6dl_timer_init_dt);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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