Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Faraday Technology FTTMR010 timer driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Based on a rewrite of arch/arm/mach-gemini/timer.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2001-2006 Storlink, Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * Register definitions common for all the timer variants.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define TIMER1_COUNT		(0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define TIMER1_LOAD		(0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define TIMER1_MATCH1		(0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define TIMER1_MATCH2		(0x0c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define TIMER2_COUNT		(0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define TIMER2_LOAD		(0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define TIMER2_MATCH1		(0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define TIMER2_MATCH2		(0x1c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define TIMER3_COUNT		(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define TIMER3_LOAD		(0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define TIMER3_MATCH1		(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define TIMER3_MATCH2		(0x2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define TIMER_CR		(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * Control register set to clear for ast2600 only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define AST2600_TIMER_CR_CLR	(0x3c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  * Control register (TMC30) bit fields for fttmr010/gemini/moxart timers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define TIMER_1_CR_ENABLE	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define TIMER_1_CR_CLOCK	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define TIMER_1_CR_INT		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define TIMER_2_CR_ENABLE	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define TIMER_2_CR_CLOCK	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define TIMER_2_CR_INT		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define TIMER_3_CR_ENABLE	BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define TIMER_3_CR_CLOCK	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define TIMER_3_CR_INT		BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define TIMER_1_CR_UPDOWN	BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define TIMER_2_CR_UPDOWN	BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define TIMER_3_CR_UPDOWN	BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  * Control register (TMC30) bit fields for aspeed ast2400/ast2500 timers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  * The aspeed timers move bits around in the control register and lacks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  * bits for setting the timer to count upwards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define TIMER_1_CR_ASPEED_ENABLE	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define TIMER_1_CR_ASPEED_CLOCK		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define TIMER_1_CR_ASPEED_INT		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define TIMER_2_CR_ASPEED_ENABLE	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define TIMER_2_CR_ASPEED_CLOCK		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define TIMER_2_CR_ASPEED_INT		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define TIMER_3_CR_ASPEED_ENABLE	BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define TIMER_3_CR_ASPEED_CLOCK		BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define TIMER_3_CR_ASPEED_INT		BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  * Interrupt status/mask register definitions for fttmr010/gemini/moxart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  * timers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  * The registers don't exist and they are not needed on aspeed timers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  * because:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  *   - aspeed timer overflow interrupt is controlled by bits in Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  *     Register (TMC30).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  *   - aspeed timers always generate interrupt when either one of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84)  *     Match registers equals to Status register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define TIMER_INTR_STATE	(0x34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define TIMER_INTR_MASK		(0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define TIMER_1_INT_MATCH1	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define TIMER_1_INT_MATCH2	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define TIMER_1_INT_OVERFLOW	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define TIMER_2_INT_MATCH1	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define TIMER_2_INT_MATCH2	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define TIMER_2_INT_OVERFLOW	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define TIMER_3_INT_MATCH1	BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define TIMER_3_INT_MATCH2	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define TIMER_3_INT_OVERFLOW	BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define TIMER_INT_ALL_MASK	0x1ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) struct fttmr010 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	unsigned int tick_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	bool is_aspeed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	u32 t1_enable_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	struct clock_event_device clkevt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	int (*timer_shutdown)(struct clock_event_device *evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #ifdef CONFIG_ARM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	struct delay_timer delay_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)  * A local singleton used by sched_clock and delay timer reads, which are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)  * fast and stateless
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static struct fttmr010 *local_fttmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static inline struct fttmr010 *to_fttmr010(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	return container_of(evt, struct fttmr010, clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static unsigned long fttmr010_read_current_timer_up(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	return readl(local_fttmr->base + TIMER2_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static unsigned long fttmr010_read_current_timer_down(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	return ~readl(local_fttmr->base + TIMER2_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static u64 notrace fttmr010_read_sched_clock_up(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	return fttmr010_read_current_timer_up();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static u64 notrace fttmr010_read_sched_clock_down(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	return fttmr010_read_current_timer_down();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int fttmr010_timer_set_next_event(unsigned long cycles,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 				       struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	struct fttmr010 *fttmr010 = to_fttmr010(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	u32 cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	/* Stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	fttmr010->timer_shutdown(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	if (fttmr010->is_aspeed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		 * ASPEED Timer Controller will load TIMER1_LOAD register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		 * into TIMER1_COUNT register when the timer is re-enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		writel(cycles, fttmr010->base + TIMER1_LOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		/* Setup the match register forward in time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		cr = readl(fttmr010->base + TIMER1_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		writel(cr + cycles, fttmr010->base + TIMER1_MATCH1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	/* Start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	cr = readl(fttmr010->base + TIMER_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	cr |= fttmr010->t1_enable_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	writel(cr, fttmr010->base + TIMER_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static int ast2600_timer_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	struct fttmr010 *fttmr010 = to_fttmr010(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	/* Stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	writel(fttmr010->t1_enable_val, fttmr010->base + AST2600_TIMER_CR_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int fttmr010_timer_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	struct fttmr010 *fttmr010 = to_fttmr010(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	u32 cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	/* Stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	cr = readl(fttmr010->base + TIMER_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	cr &= ~fttmr010->t1_enable_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	writel(cr, fttmr010->base + TIMER_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int fttmr010_timer_set_oneshot(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	struct fttmr010 *fttmr010 = to_fttmr010(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	u32 cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	/* Stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	fttmr010->timer_shutdown(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	/* Setup counter start from 0 or ~0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	writel(0, fttmr010->base + TIMER1_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	if (fttmr010->is_aspeed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		writel(~0, fttmr010->base + TIMER1_LOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		writel(0, fttmr010->base + TIMER1_LOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		/* Enable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		cr = readl(fttmr010->base + TIMER_INTR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		cr &= ~(TIMER_1_INT_OVERFLOW | TIMER_1_INT_MATCH2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		cr |= TIMER_1_INT_MATCH1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		writel(cr, fttmr010->base + TIMER_INTR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int fttmr010_timer_set_periodic(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	struct fttmr010 *fttmr010 = to_fttmr010(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	u32 period = DIV_ROUND_CLOSEST(fttmr010->tick_rate, HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	u32 cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	/* Stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	fttmr010->timer_shutdown(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	/* Setup timer to fire at 1/HZ intervals. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	if (fttmr010->is_aspeed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		writel(period, fttmr010->base + TIMER1_LOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		cr = 0xffffffff - (period - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		writel(cr, fttmr010->base + TIMER1_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		writel(cr, fttmr010->base + TIMER1_LOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		/* Enable interrupt on overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		cr = readl(fttmr010->base + TIMER_INTR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		cr &= ~(TIMER_1_INT_MATCH1 | TIMER_1_INT_MATCH2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		cr |= TIMER_1_INT_OVERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		writel(cr, fttmr010->base + TIMER_INTR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	/* Start the timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	cr = readl(fttmr010->base + TIMER_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	cr |= fttmr010->t1_enable_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	writel(cr, fttmr010->base + TIMER_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)  * IRQ handler for the timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static irqreturn_t fttmr010_timer_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	struct clock_event_device *evt = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	evt->event_handler(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static irqreturn_t ast2600_timer_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	struct clock_event_device *evt = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	struct fttmr010 *fttmr010 = to_fttmr010(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	writel(0x1, fttmr010->base + TIMER_INTR_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	evt->event_handler(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static int __init fttmr010_common_init(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		bool is_aspeed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		int (*timer_shutdown)(struct clock_event_device *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		irq_handler_t irq_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	struct fttmr010 *fttmr010;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	 * These implementations require a clock reference.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	 * FIXME: we currently only support clocking using PCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	 * and using EXTCLK is not supported in the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	clk = of_clk_get_by_name(np, "PCLK");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		pr_err("could not get PCLK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		pr_err("failed to enable PCLK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	fttmr010 = kzalloc(sizeof(*fttmr010), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	if (!fttmr010) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		goto out_disable_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	fttmr010->tick_rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	fttmr010->base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	if (!fttmr010->base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		pr_err("Can't remap registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	/* IRQ for timer 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	irq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	if (irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		pr_err("Can't parse IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		goto out_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	 * The Aspeed timers move bits around in the control register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	if (is_aspeed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		fttmr010->t1_enable_val = TIMER_1_CR_ASPEED_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 			TIMER_1_CR_ASPEED_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		fttmr010->is_aspeed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		fttmr010->t1_enable_val = TIMER_1_CR_ENABLE | TIMER_1_CR_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		 * Reset the interrupt mask and status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		writel(TIMER_INT_ALL_MASK, fttmr010->base + TIMER_INTR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		writel(0, fttmr010->base + TIMER_INTR_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	 * Enable timer 1 count up, timer 2 count up, except on Aspeed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	 * where everything just counts down.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	if (is_aspeed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		val = TIMER_2_CR_ASPEED_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		val = TIMER_2_CR_ENABLE | TIMER_1_CR_UPDOWN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 			TIMER_2_CR_UPDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	writel(val, fttmr010->base + TIMER_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	 * Setup free-running clocksource timer (interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	 * disabled.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	local_fttmr = fttmr010;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	writel(0, fttmr010->base + TIMER2_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	writel(0, fttmr010->base + TIMER2_MATCH1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	writel(0, fttmr010->base + TIMER2_MATCH2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	if (fttmr010->is_aspeed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		writel(~0, fttmr010->base + TIMER2_LOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		clocksource_mmio_init(fttmr010->base + TIMER2_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 				      "FTTMR010-TIMER2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 				      fttmr010->tick_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 				      300, 32, clocksource_mmio_readl_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		sched_clock_register(fttmr010_read_sched_clock_down, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 				     fttmr010->tick_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		writel(0, fttmr010->base + TIMER2_LOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		clocksource_mmio_init(fttmr010->base + TIMER2_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 				      "FTTMR010-TIMER2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 				      fttmr010->tick_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 				      300, 32, clocksource_mmio_readl_up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		sched_clock_register(fttmr010_read_sched_clock_up, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 				     fttmr010->tick_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	fttmr010->timer_shutdown = timer_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	 * Setup clockevent timer (interrupt-driven) on timer 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	writel(0, fttmr010->base + TIMER1_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	writel(0, fttmr010->base + TIMER1_LOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	writel(0, fttmr010->base + TIMER1_MATCH1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	writel(0, fttmr010->base + TIMER1_MATCH2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	ret = request_irq(irq, irq_handler, IRQF_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 			  "FTTMR010-TIMER1", &fttmr010->clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		pr_err("FTTMR010-TIMER1 no IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		goto out_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	fttmr010->clkevt.name = "FTTMR010-TIMER1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	/* Reasonably fast and accurate clock event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	fttmr010->clkevt.rating = 300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	fttmr010->clkevt.features = CLOCK_EVT_FEAT_PERIODIC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		CLOCK_EVT_FEAT_ONESHOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	fttmr010->clkevt.set_next_event = fttmr010_timer_set_next_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	fttmr010->clkevt.set_state_shutdown = fttmr010->timer_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	fttmr010->clkevt.set_state_periodic = fttmr010_timer_set_periodic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	fttmr010->clkevt.set_state_oneshot = fttmr010_timer_set_oneshot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	fttmr010->clkevt.tick_resume = fttmr010->timer_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	fttmr010->clkevt.cpumask = cpumask_of(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	fttmr010->clkevt.irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	clockevents_config_and_register(&fttmr010->clkevt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 					fttmr010->tick_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 					1, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #ifdef CONFIG_ARM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	/* Also use this timer for delays */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	if (fttmr010->is_aspeed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		fttmr010->delay_timer.read_current_timer =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 			fttmr010_read_current_timer_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		fttmr010->delay_timer.read_current_timer =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 			fttmr010_read_current_timer_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	fttmr010->delay_timer.freq = fttmr010->tick_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	register_current_timer_delay(&fttmr010->delay_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) out_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	iounmap(fttmr010->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	kfree(fttmr010);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) out_disable_clock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static __init int ast2600_timer_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	return fttmr010_common_init(np, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 			ast2600_timer_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 			ast2600_timer_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static __init int aspeed_timer_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	return fttmr010_common_init(np, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 			fttmr010_timer_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 			fttmr010_timer_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static __init int fttmr010_timer_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	return fttmr010_common_init(np, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 			fttmr010_timer_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 			fttmr010_timer_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) TIMER_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) TIMER_OF_DECLARE(gemini, "cortina,gemini-timer", fttmr010_timer_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) TIMER_OF_DECLARE(moxart, "moxa,moxart-timer", fttmr010_timer_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) TIMER_OF_DECLARE(ast2400, "aspeed,ast2400-timer", aspeed_timer_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) TIMER_OF_DECLARE(ast2500, "aspeed,ast2500-timer", aspeed_timer_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) TIMER_OF_DECLARE(ast2600, "aspeed,ast2600-timer", ast2600_timer_init);