^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Freescale FlexTimer Module (FTM) timer driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2014 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/fsl/ftm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define FTM_SC_CLK(c) ((c) << FTM_SC_CLK_MASK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct ftm_clock_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) void __iomem *clksrc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) void __iomem *clkevt_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) unsigned long periodic_cyc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) unsigned long ps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) bool big_endian;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static struct ftm_clock_device *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static inline u32 ftm_readl(void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) if (priv->big_endian)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) return ioread32be(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return ioread32(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static inline void ftm_writel(u32 val, void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (priv->big_endian)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) iowrite32be(val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) iowrite32(val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static inline void ftm_counter_enable(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* select and enable counter clock source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) val = ftm_readl(base + FTM_SC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) val &= ~(FTM_SC_PS_MASK | FTM_SC_CLK_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) val |= priv->ps | FTM_SC_CLK(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ftm_writel(val, base + FTM_SC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static inline void ftm_counter_disable(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* disable counter clock source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) val = ftm_readl(base + FTM_SC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) val &= ~(FTM_SC_PS_MASK | FTM_SC_CLK_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ftm_writel(val, base + FTM_SC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static inline void ftm_irq_acknowledge(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) val = ftm_readl(base + FTM_SC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) val &= ~FTM_SC_TOF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ftm_writel(val, base + FTM_SC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static inline void ftm_irq_enable(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) val = ftm_readl(base + FTM_SC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) val |= FTM_SC_TOIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ftm_writel(val, base + FTM_SC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static inline void ftm_irq_disable(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) val = ftm_readl(base + FTM_SC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) val &= ~FTM_SC_TOIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ftm_writel(val, base + FTM_SC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static inline void ftm_reset_counter(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * The CNT register contains the FTM counter value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * Reset clears the CNT register. Writing any value to COUNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * updates the counter with its initial value, CNTIN.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ftm_writel(0x00, base + FTM_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static u64 notrace ftm_read_sched_clock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return ftm_readl(priv->clksrc_base + FTM_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int ftm_set_next_event(unsigned long delta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct clock_event_device *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * The CNNIN and MOD are all double buffer registers, writing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * to the MOD register latches the value into a buffer. The MOD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * register is updated with the value of its write buffer with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * the following scenario:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * a, the counter source clock is diabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ftm_counter_disable(priv->clkevt_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Force the value of CNTIN to be loaded into the FTM counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ftm_reset_counter(priv->clkevt_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * The counter increments until the value of MOD is reached,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * at which point the counter is reloaded with the value of CNTIN.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * The TOF (the overflow flag) bit is set when the FTM counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * changes from MOD to CNTIN. So we should using the delta - 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ftm_writel(delta - 1, priv->clkevt_base + FTM_MOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ftm_counter_enable(priv->clkevt_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ftm_irq_enable(priv->clkevt_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int ftm_set_oneshot(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ftm_counter_disable(priv->clkevt_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int ftm_set_periodic(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ftm_set_next_event(priv->periodic_cyc, evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static irqreturn_t ftm_evt_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct clock_event_device *evt = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ftm_irq_acknowledge(priv->clkevt_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (likely(clockevent_state_oneshot(evt))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ftm_irq_disable(priv->clkevt_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ftm_counter_disable(priv->clkevt_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) evt->event_handler(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static struct clock_event_device ftm_clockevent = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .name = "Freescale ftm timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .features = CLOCK_EVT_FEAT_PERIODIC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) CLOCK_EVT_FEAT_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .set_state_periodic = ftm_set_periodic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .set_state_oneshot = ftm_set_oneshot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .set_next_event = ftm_set_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .rating = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int __init ftm_clockevent_init(unsigned long freq, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ftm_writel(0x00, priv->clkevt_base + FTM_CNTIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ftm_writel(~0u, priv->clkevt_base + FTM_MOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ftm_reset_counter(priv->clkevt_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) err = request_irq(irq, ftm_evt_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) "Freescale ftm timer", &ftm_clockevent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) pr_err("ftm: setup irq failed: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ftm_clockevent.cpumask = cpumask_of(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ftm_clockevent.irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) clockevents_config_and_register(&ftm_clockevent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) freq / (1 << priv->ps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 1, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ftm_counter_enable(priv->clkevt_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int __init ftm_clocksource_init(unsigned long freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ftm_writel(0x00, priv->clksrc_base + FTM_CNTIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ftm_writel(~0u, priv->clksrc_base + FTM_MOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ftm_reset_counter(priv->clksrc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) sched_clock_register(ftm_read_sched_clock, 16, freq / (1 << priv->ps));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) err = clocksource_mmio_init(priv->clksrc_base + FTM_CNT, "fsl-ftm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) freq / (1 << priv->ps), 300, 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) clocksource_mmio_readl_up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) pr_err("ftm: init clock source mmio failed: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ftm_counter_enable(priv->clksrc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int __init __ftm_clk_init(struct device_node *np, char *cnt_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) char *ftm_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) clk = of_clk_get_by_name(np, cnt_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) pr_err("ftm: Cannot get \"%s\": %ld\n", cnt_name, PTR_ERR(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) err = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) pr_err("ftm: clock failed to prepare+enable \"%s\": %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) cnt_name, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) clk = of_clk_get_by_name(np, ftm_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) pr_err("ftm: Cannot get \"%s\": %ld\n", ftm_name, PTR_ERR(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) err = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) pr_err("ftm: clock failed to prepare+enable \"%s\": %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ftm_name, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static unsigned long __init ftm_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) long freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) freq = __ftm_clk_init(np, "ftm-evt-counter-en", "ftm-evt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (freq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) freq = __ftm_clk_init(np, "ftm-src-counter-en", "ftm-src");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (freq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int __init ftm_calc_closest_round_cyc(unsigned long freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) priv->ps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* The counter register is only using the lower 16 bits, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * if the 'freq' value is to big here, then the periodic_cyc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * may exceed 0xFFFF.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) priv->periodic_cyc = DIV_ROUND_CLOSEST(freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) HZ * (1 << priv->ps++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) } while (priv->periodic_cyc > 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (priv->ps > FTM_PS_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) pr_err("ftm: the prescaler is %lu > %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) priv->ps, FTM_PS_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static int __init ftm_timer_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned long freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) priv = kzalloc(sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) priv->clkevt_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (!priv->clkevt_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) pr_err("ftm: unable to map event timer registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) goto err_clkevt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) priv->clksrc_base = of_iomap(np, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (!priv->clksrc_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) pr_err("ftm: unable to map source timer registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) goto err_clksrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) irq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) pr_err("ftm: unable to get IRQ from DT, %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) priv->big_endian = of_property_read_bool(np, "big-endian");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) freq = ftm_clk_init(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (!freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ret = ftm_calc_closest_round_cyc(freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ret = ftm_clocksource_init(freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ret = ftm_clockevent_init(freq, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) iounmap(priv->clksrc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) err_clksrc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) iounmap(priv->clkevt_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) err_clkevt:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) kfree(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) TIMER_OF_DECLARE(flextimer, "fsl,ftm-timer", ftm_timer_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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