^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * TI DaVinci clocksource driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2019 Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Bartosz Golaszewski <bgolaszewski@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * (with tiny parts adopted from code by Kevin Hilman <khilman@baylibre.com>)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <clocksource/timer-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #undef pr_fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define pr_fmt(fmt) "%s: " fmt, __func__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DAVINCI_TIMER_REG_TIM12 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DAVINCI_TIMER_REG_TIM34 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DAVINCI_TIMER_REG_PRD12 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DAVINCI_TIMER_REG_PRD34 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DAVINCI_TIMER_REG_TCR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DAVINCI_TIMER_REG_TGCR 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DAVINCI_TIMER_TIMMODE_MASK GENMASK(3, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DAVINCI_TIMER_RESET_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DAVINCI_TIMER_TIMMODE_32BIT_UNCHAINED BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DAVINCI_TIMER_UNRESET GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DAVINCI_TIMER_ENAMODE_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DAVINCI_TIMER_ENAMODE_DISABLED 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DAVINCI_TIMER_ENAMODE_ONESHOT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DAVINCI_TIMER_ENAMODE_PERIODIC BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DAVINCI_TIMER_ENAMODE_SHIFT_TIM12 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DAVINCI_TIMER_ENAMODE_SHIFT_TIM34 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DAVINCI_TIMER_MIN_DELTA 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DAVINCI_TIMER_MAX_DELTA 0xfffffffe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DAVINCI_TIMER_CLKSRC_BITS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DAVINCI_TIMER_TGCR_DEFAULT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) (DAVINCI_TIMER_TIMMODE_32BIT_UNCHAINED | DAVINCI_TIMER_UNRESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct davinci_clockevent {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct clock_event_device dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned int cmp_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * This must be globally accessible by davinci_timer_read_sched_clock(), so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * let's keep it here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct clocksource dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned int tim_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) } davinci_clocksource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static struct davinci_clockevent *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) to_davinci_clockevent(struct clock_event_device *clockevent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return container_of(clockevent, struct davinci_clockevent, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) davinci_clockevent_read(struct davinci_clockevent *clockevent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return readl_relaxed(clockevent->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static void davinci_clockevent_write(struct davinci_clockevent *clockevent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned int reg, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) writel_relaxed(val, clockevent->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static void davinci_tim12_shutdown(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned int tcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) tcr = DAVINCI_TIMER_ENAMODE_DISABLED <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) DAVINCI_TIMER_ENAMODE_SHIFT_TIM12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * This function is only ever called if we're using both timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * halves. In this case TIM34 runs in periodic mode and we must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * not modify it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) tcr |= DAVINCI_TIMER_ENAMODE_PERIODIC <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) DAVINCI_TIMER_ENAMODE_SHIFT_TIM34;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static void davinci_tim12_set_oneshot(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned int tcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) tcr = DAVINCI_TIMER_ENAMODE_ONESHOT <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) DAVINCI_TIMER_ENAMODE_SHIFT_TIM12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Same as above. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) tcr |= DAVINCI_TIMER_ENAMODE_PERIODIC <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) DAVINCI_TIMER_ENAMODE_SHIFT_TIM34;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int davinci_clockevent_shutdown(struct clock_event_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct davinci_clockevent *clockevent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) clockevent = to_davinci_clockevent(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) davinci_tim12_shutdown(clockevent->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static int davinci_clockevent_set_oneshot(struct clock_event_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct davinci_clockevent *clockevent = to_davinci_clockevent(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) davinci_clockevent_write(clockevent, DAVINCI_TIMER_REG_TIM12, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) davinci_tim12_set_oneshot(clockevent->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) davinci_clockevent_set_next_event_std(unsigned long cycles,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct clock_event_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct davinci_clockevent *clockevent = to_davinci_clockevent(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) davinci_clockevent_shutdown(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) davinci_clockevent_write(clockevent, DAVINCI_TIMER_REG_TIM12, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) davinci_clockevent_write(clockevent, DAVINCI_TIMER_REG_PRD12, cycles);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) davinci_clockevent_set_oneshot(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) davinci_clockevent_set_next_event_cmp(unsigned long cycles,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct clock_event_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct davinci_clockevent *clockevent = to_davinci_clockevent(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned int curr_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) curr_time = davinci_clockevent_read(clockevent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) DAVINCI_TIMER_REG_TIM12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) davinci_clockevent_write(clockevent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) clockevent->cmp_off, curr_time + cycles);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static irqreturn_t davinci_timer_irq_timer(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct davinci_clockevent *clockevent = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (!clockevent_state_oneshot(&clockevent->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) davinci_tim12_shutdown(clockevent->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) clockevent->dev.event_handler(&clockevent->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static u64 notrace davinci_timer_read_sched_clock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return readl_relaxed(davinci_clocksource.base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) davinci_clocksource.tim_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static u64 davinci_clocksource_read(struct clocksource *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return davinci_timer_read_sched_clock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * Standard use-case: we're using tim12 for clockevent and tim34 for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * clocksource. The default is making the former run in oneshot mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * and the latter in periodic mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static void davinci_clocksource_init_tim34(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int tcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) tcr = DAVINCI_TIMER_ENAMODE_PERIODIC <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) DAVINCI_TIMER_ENAMODE_SHIFT_TIM34;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) tcr |= DAVINCI_TIMER_ENAMODE_ONESHOT <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) DAVINCI_TIMER_ENAMODE_SHIFT_TIM12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) writel_relaxed(UINT_MAX, base + DAVINCI_TIMER_REG_PRD34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * Special use-case on da830: the DSP may use tim34. We're using tim12 for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * both clocksource and clockevent. We set tim12 to periodic and don't touch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * tim34.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static void davinci_clocksource_init_tim12(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) unsigned int tcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) tcr = DAVINCI_TIMER_ENAMODE_PERIODIC <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) DAVINCI_TIMER_ENAMODE_SHIFT_TIM12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) writel_relaxed(UINT_MAX, base + DAVINCI_TIMER_REG_PRD12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static void davinci_timer_init(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* Set clock to internal mode and disable it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * Reset both 32-bit timers, set no prescaler for timer 34, set the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * timer to dual 32-bit unchained mode, unreset both 32-bit timers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) writel_relaxed(DAVINCI_TIMER_TGCR_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) base + DAVINCI_TIMER_REG_TGCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* Init both counters to zero. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int __init davinci_timer_register(struct clk *clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) const struct davinci_timer_cfg *timer_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct davinci_clockevent *clockevent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) unsigned int tick_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) rv = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (rv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) pr_err("Unable to prepare and enable the timer clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (!request_mem_region(timer_cfg->reg.start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) resource_size(&timer_cfg->reg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) "davinci-timer")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) pr_err("Unable to request memory region\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) base = ioremap(timer_cfg->reg.start, resource_size(&timer_cfg->reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) pr_err("Unable to map the register range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) davinci_timer_init(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) tick_rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) clockevent = kzalloc(sizeof(*clockevent), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (!clockevent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) clockevent->dev.name = "tim12";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) clockevent->dev.features = CLOCK_EVT_FEAT_ONESHOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) clockevent->dev.cpumask = cpumask_of(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) clockevent->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (timer_cfg->cmp_off) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) clockevent->cmp_off = timer_cfg->cmp_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) clockevent->dev.set_next_event =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) davinci_clockevent_set_next_event_cmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) clockevent->dev.set_next_event =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) davinci_clockevent_set_next_event_std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) clockevent->dev.set_state_oneshot =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) davinci_clockevent_set_oneshot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) clockevent->dev.set_state_shutdown =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) davinci_clockevent_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) rv = request_irq(timer_cfg->irq[DAVINCI_TIMER_CLOCKEVENT_IRQ].start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) davinci_timer_irq_timer, IRQF_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) "clockevent/tim12", clockevent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (rv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) pr_err("Unable to request the clockevent interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) davinci_clocksource.dev.rating = 300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) davinci_clocksource.dev.read = davinci_clocksource_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) davinci_clocksource.dev.mask =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) CLOCKSOURCE_MASK(DAVINCI_TIMER_CLKSRC_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) davinci_clocksource.dev.flags = CLOCK_SOURCE_IS_CONTINUOUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) davinci_clocksource.base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (timer_cfg->cmp_off) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) davinci_clocksource.dev.name = "tim12";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) davinci_clocksource.tim_off = DAVINCI_TIMER_REG_TIM12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) davinci_clocksource_init_tim12(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) davinci_clocksource.dev.name = "tim34";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) davinci_clocksource.tim_off = DAVINCI_TIMER_REG_TIM34;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) davinci_clocksource_init_tim34(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) clockevents_config_and_register(&clockevent->dev, tick_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) DAVINCI_TIMER_MIN_DELTA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) DAVINCI_TIMER_MAX_DELTA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) rv = clocksource_register_hz(&davinci_clocksource.dev, tick_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (rv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) pr_err("Unable to register clocksource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) sched_clock_register(davinci_timer_read_sched_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) DAVINCI_TIMER_CLKSRC_BITS, tick_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int __init of_davinci_timer_register(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct davinci_timer_cfg timer_cfg = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) int rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) rv = of_address_to_resource(np, 0, &timer_cfg.reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (rv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) pr_err("Unable to get the register range for timer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) rv = of_irq_to_resource_table(np, timer_cfg.irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) DAVINCI_TIMER_NUM_IRQS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (rv != DAVINCI_TIMER_NUM_IRQS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) pr_err("Unable to get the interrupts for timer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) clk = of_clk_get(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) pr_err("Unable to get the timer clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) rv = davinci_timer_register(clk, &timer_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (rv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) TIMER_OF_DECLARE(davinci_timer, "ti,da830-timer", of_davinci_timer_register);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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