^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Clock event driver for the CS5535/CS5536
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2006, Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2007 Andres Salomon <dilinger@debian.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2009 Andres Salomon <dilinger@collabora.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * The MFGPTs are documented in AMD Geode CS5536 Companion Device Data Book.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/cs5535.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DRV_NAME "cs5535-clockevt"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static int timer_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) module_param_hw_named(irq, timer_irq, int, irq, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) MODULE_PARM_DESC(irq, "Which IRQ to use for the clock source MFGPT ticks.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * We are using the 32.768kHz input clock - it's the only one that has the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * ranges we find desirable. The following table lists the suitable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * divisors and the associated Hz, minimum interval and the maximum interval:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * Divisor Hz Min Delta (s) Max Delta (s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * 1 32768 .00048828125 2.000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * 2 16384 .0009765625 4.000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * 4 8192 .001953125 8.000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * 8 4096 .00390625 16.000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * 16 2048 .0078125 32.000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * 32 1024 .015625 64.000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * 64 512 .03125 128.000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * 128 256 .0625 256.000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * 256 128 .125 512.000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static struct cs5535_mfgpt_timer *cs5535_event_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Selected from the table above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MFGPT_DIVISOR 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MFGPT_SCALE 4 /* divisor = 2^(scale) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MFGPT_HZ (32768 / MFGPT_DIVISOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MFGPT_PERIODIC (MFGPT_HZ / HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * The MFGPT timers on the CS5536 provide us with suitable timers to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * as clock event sources - not as good as a HPET or APIC, but certainly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * better than the PIT. This isn't a general purpose MFGPT driver, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * a simplified one designed specifically to act as a clock event source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * For full details about the MFGPT, please consult the CS5536 data sheet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static void disable_timer(struct cs5535_mfgpt_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* avoid races by clearing CMP1 and CMP2 unconditionally */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) cs5535_mfgpt_write(timer, MFGPT_REG_SETUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) (uint16_t) ~MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) MFGPT_SETUP_CMP2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static void start_timer(struct cs5535_mfgpt_timer *timer, uint16_t delta)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) cs5535_mfgpt_write(timer, MFGPT_REG_CMP2, delta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) cs5535_mfgpt_write(timer, MFGPT_REG_COUNTER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) cs5535_mfgpt_write(timer, MFGPT_REG_SETUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static int mfgpt_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) disable_timer(cs5535_event_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static int mfgpt_set_periodic(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) disable_timer(cs5535_event_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) start_timer(cs5535_event_clock, MFGPT_PERIODIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static int mfgpt_next_event(unsigned long delta, struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) start_timer(cs5535_event_clock, delta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static struct clock_event_device cs5535_clockevent = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .set_state_shutdown = mfgpt_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .set_state_periodic = mfgpt_set_periodic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .set_state_oneshot = mfgpt_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .tick_resume = mfgpt_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .set_next_event = mfgpt_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .rating = 250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static irqreturn_t mfgpt_tick(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) uint16_t val = cs5535_mfgpt_read(cs5535_event_clock, MFGPT_REG_SETUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* See if the interrupt was for us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (!(val & (MFGPT_SETUP_SETUP | MFGPT_SETUP_CMP2 | MFGPT_SETUP_CMP1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Turn off the clock (and clear the event) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) disable_timer(cs5535_event_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (clockevent_state_detached(&cs5535_clockevent) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) clockevent_state_shutdown(&cs5535_clockevent))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Clear the counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) cs5535_mfgpt_write(cs5535_event_clock, MFGPT_REG_COUNTER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Restart the clock in periodic mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (clockevent_state_periodic(&cs5535_clockevent))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) cs5535_mfgpt_write(cs5535_event_clock, MFGPT_REG_SETUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) cs5535_clockevent.event_handler(&cs5535_clockevent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int __init cs5535_mfgpt_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned long flags = IRQF_NOBALANCING | IRQF_TIMER | IRQF_SHARED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct cs5535_mfgpt_timer *timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) uint16_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) timer = cs5535_mfgpt_alloc_timer(MFGPT_TIMER_ANY, MFGPT_DOMAIN_WORKING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (!timer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) printk(KERN_ERR DRV_NAME ": Could not allocate MFGPT timer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) cs5535_event_clock = timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Set up the IRQ on the MFGPT side */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (cs5535_mfgpt_setup_irq(timer, MFGPT_CMP2, &timer_irq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) printk(KERN_ERR DRV_NAME ": Could not set up IRQ %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) timer_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) goto err_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* And register it with the kernel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ret = request_irq(timer_irq, mfgpt_tick, flags, DRV_NAME, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) printk(KERN_ERR DRV_NAME ": Unable to set up the interrupt.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) goto err_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* Set the clock scale and enable the event mode for CMP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) val = MFGPT_SCALE | (3 << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) cs5535_mfgpt_write(cs5535_event_clock, MFGPT_REG_SETUP, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Set up the clock event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) printk(KERN_INFO DRV_NAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ": Registering MFGPT timer as a clock event, using IRQ %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) timer_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) clockevents_config_and_register(&cs5535_clockevent, MFGPT_HZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 0xF, 0xFFFE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) err_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) cs5535_mfgpt_release_irq(cs5535_event_clock, MFGPT_CMP2, &timer_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) err_timer:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) cs5535_mfgpt_free_timer(cs5535_event_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) printk(KERN_ERR DRV_NAME ": Unable to set up the MFGPT clock source\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) module_init(cs5535_mfgpt_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) MODULE_AUTHOR("Andres Salomon <dilinger@queued.net>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) MODULE_DESCRIPTION("CS5535/CS5536 MFGPT clock event driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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