Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2020 Western Digital Corporation or its affiliates.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * CLINT MMIO timer device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define pr_fmt(fmt) "clint: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/io-64-nonatomic-lo-hi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/timex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #ifndef CONFIG_RISCV_M_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <asm/clint.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define CLINT_IPI_OFF		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define CLINT_TIMER_CMP_OFF	0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define CLINT_TIMER_VAL_OFF	0xbff8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /* CLINT manages IPI and Timer for RISC-V M-mode  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) static u32 __iomem *clint_ipi_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) static u64 __iomem *clint_timer_cmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) static u64 __iomem *clint_timer_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static unsigned long clint_timer_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static unsigned int clint_timer_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #ifdef CONFIG_RISCV_M_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) u64 __iomem *clint_time_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) EXPORT_SYMBOL(clint_time_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static void clint_send_ipi(const struct cpumask *target)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	unsigned int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	for_each_cpu(cpu, target)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		writel(1, clint_ipi_base + cpuid_to_hartid_map(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static void clint_clear_ipi(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	writel(0, clint_ipi_base + cpuid_to_hartid_map(smp_processor_id()));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static struct riscv_ipi_ops clint_ipi_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	.ipi_inject = clint_send_ipi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	.ipi_clear = clint_clear_ipi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define clint_get_cycles()	readq_relaxed(clint_timer_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define clint_get_cycles()	readl_relaxed(clint_timer_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define clint_get_cycles_hi()	readl_relaxed(((u32 *)clint_timer_val) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) static u64 notrace clint_get_cycles64(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	return clint_get_cycles();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #else /* CONFIG_64BIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static u64 notrace clint_get_cycles64(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	u32 hi, lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		hi = clint_get_cycles_hi();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		lo = clint_get_cycles();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	} while (hi != clint_get_cycles_hi());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	return ((u64)hi << 32) | lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #endif /* CONFIG_64BIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static u64 clint_rdtime(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	return clint_get_cycles64();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static struct clocksource clint_clocksource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	.name		= "clint_clocksource",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	.rating		= 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	.mask		= CLOCKSOURCE_MASK(64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	.read		= clint_rdtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int clint_clock_next_event(unsigned long delta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 				   struct clock_event_device *ce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	void __iomem *r = clint_timer_cmp +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 			  cpuid_to_hartid_map(smp_processor_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	csr_set(CSR_IE, IE_TIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	writeq_relaxed(clint_get_cycles64() + delta, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static DEFINE_PER_CPU(struct clock_event_device, clint_clock_event) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	.name		= "clint_clockevent",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	.features	= CLOCK_EVT_FEAT_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	.rating		= 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	.set_next_event	= clint_clock_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int clint_timer_starting_cpu(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	struct clock_event_device *ce = per_cpu_ptr(&clint_clock_event, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	ce->cpumask = cpumask_of(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	clockevents_config_and_register(ce, clint_timer_freq, 100, 0x7fffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	enable_percpu_irq(clint_timer_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 			  irq_get_trigger_type(clint_timer_irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int clint_timer_dying_cpu(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	disable_percpu_irq(clint_timer_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static irqreturn_t clint_timer_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	struct clock_event_device *evdev = this_cpu_ptr(&clint_clock_event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	csr_clear(CSR_IE, IE_TIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	evdev->event_handler(evdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int __init clint_timer_init_dt(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	u32 i, nr_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	struct of_phandle_args oirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	 * Ensure that CLINT device interrupts are either RV_IRQ_TIMER or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	 * RV_IRQ_SOFT. If it's anything else then we ignore the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	nr_irqs = of_irq_count(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	for (i = 0; i < nr_irqs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		if (of_irq_parse_one(np, i, &oirq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			pr_err("%pOFP: failed to parse irq %d.\n", np, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		if ((oirq.args_count != 1) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		    (oirq.args[0] != RV_IRQ_TIMER &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		     oirq.args[0] != RV_IRQ_SOFT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 			pr_err("%pOFP: invalid irq %d (hwirq %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			       np, i, oirq.args[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		/* Find parent irq domain and map timer irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		if (!clint_timer_irq &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		    oirq.args[0] == RV_IRQ_TIMER &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		    irq_find_host(oirq.np))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			clint_timer_irq = irq_of_parse_and_map(np, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	/* If CLINT timer irq not found then fail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	if (!clint_timer_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		pr_err("%pOFP: timer irq not found\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		pr_err("%pOFP: could not map registers\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	clint_ipi_base = base + CLINT_IPI_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	clint_timer_cmp = base + CLINT_TIMER_CMP_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	clint_timer_val = base + CLINT_TIMER_VAL_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	clint_timer_freq = riscv_timebase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #ifdef CONFIG_RISCV_M_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	 * Yes, that's an odd naming scheme.  time_val is public, but hopefully
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	 * will die in favor of something cleaner.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	clint_time_val = clint_timer_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	pr_info("%pOFP: timer running at %ld Hz\n", np, clint_timer_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	rc = clocksource_register_hz(&clint_clocksource, clint_timer_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		pr_err("%pOFP: clocksource register failed [%d]\n", np, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		goto fail_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	sched_clock_register(clint_get_cycles64, 64, clint_timer_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	rc = request_percpu_irq(clint_timer_irq, clint_timer_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 				 "clint-timer", &clint_clock_event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		pr_err("registering percpu irq failed [%d]\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		goto fail_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	rc = cpuhp_setup_state(CPUHP_AP_CLINT_TIMER_STARTING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 				"clockevents/clint/timer:starting",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 				clint_timer_starting_cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 				clint_timer_dying_cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		pr_err("%pOFP: cpuhp setup state failed [%d]\n", np, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		goto fail_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	riscv_set_ipi_ops(&clint_ipi_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	clint_clear_ipi();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) fail_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	free_irq(clint_timer_irq, &clint_clock_event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) fail_iounmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) TIMER_OF_DECLARE(clint_timer, "riscv,clint0", clint_timer_init_dt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) TIMER_OF_DECLARE(clint_timer1, "sifive,clint0", clint_timer_init_dt);