Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * This file contains driver for the Cadence Triple Timer Counter Rev 06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 2011-2013 Xilinx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * based on arch/mips/kernel/time.c timer driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * This driver configures the 2 16/32-bit count-up timers as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * T1: Timer 1, clocksource for generic timekeeping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * T2: Timer 2, clockevent source for hrtimers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * T3: Timer 3, <unused>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * The input frequency to the timer module for emulation is 2.5MHz which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * the timers are clocked at 78.125KHz (12.8 us resolution).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * The input frequency to the timer module in silicon is configurable and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * obtained from device tree. The pre-scaler of 32 is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * Timer Register Offset Definitions of Timer 1, Increment base address by 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * and use same offsets for Timer 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define TTC_CLK_CNTRL_OFFSET		0x00 /* Clock Control Reg, RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define TTC_CNT_CNTRL_OFFSET		0x0C /* Counter Control Reg, RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define TTC_COUNT_VAL_OFFSET		0x18 /* Counter Value Reg, RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define TTC_INTR_VAL_OFFSET		0x24 /* Interval Count Reg, RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define TTC_ISR_OFFSET		0x54 /* Interrupt Status Reg, RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define TTC_IER_OFFSET		0x60 /* Interrupt Enable Reg, RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define TTC_CNT_CNTRL_DISABLE_MASK	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define TTC_CLK_CNTRL_CSRC_MASK		(1 << 5)	/* clock source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define TTC_CLK_CNTRL_PSV_MASK		0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define TTC_CLK_CNTRL_PSV_SHIFT		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  * Setup the timers to use pre-scaling, using a fixed value for now that will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  * work across most input frequency, but it may need to be more dynamic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define PRESCALE_EXPONENT	11	/* 2 ^ PRESCALE_EXPONENT = PRESCALE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define PRESCALE		2048	/* The exponent must match this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define CLK_CNTRL_PRESCALE	((PRESCALE_EXPONENT - 1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define CLK_CNTRL_PRESCALE_EN	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define CNT_CNTRL_RESET		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define MAX_F_ERR 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  * struct ttc_timer - This definition defines local timer structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  * @base_addr:	Base address of timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  * @freq:	Timer input clock frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  * @clk:	Associated clock source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  * @clk_rate_change_nb	Notifier block for clock rate changes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) struct ttc_timer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	void __iomem *base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	unsigned long freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct notifier_block clk_rate_change_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define to_ttc_timer(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		container_of(x, struct ttc_timer, clk_rate_change_nb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) struct ttc_timer_clocksource {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	u32			scale_clk_ctrl_reg_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	u32			scale_clk_ctrl_reg_new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	struct ttc_timer	ttc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	struct clocksource	cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define to_ttc_timer_clksrc(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		container_of(x, struct ttc_timer_clocksource, cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) struct ttc_timer_clockevent {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	struct ttc_timer		ttc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	struct clock_event_device	ce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define to_ttc_timer_clkevent(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		container_of(x, struct ttc_timer_clockevent, ce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void __iomem *ttc_sched_clock_val_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)  * ttc_set_interval - Set the timer interval value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)  * @timer:	Pointer to the timer instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)  * @cycles:	Timer interval ticks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)  **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void ttc_set_interval(struct ttc_timer *timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 					unsigned long cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	u32 ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	/* Disable the counter, set the counter value  and re-enable counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	 * Reset the counter (0x10) so that it starts from 0, one-shot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	 * mode makes this needed for timing to be right.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	ctrl_reg |= CNT_CNTRL_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)  * ttc_clock_event_interrupt - Clock event timer interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)  * @irq:	IRQ number of the Timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)  * @dev_id:	void pointer to the ttc_timer instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)  * returns: Always IRQ_HANDLED - success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)  **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	struct ttc_timer_clockevent *ttce = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	struct ttc_timer *timer = &ttce->ttc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	/* Acknowledge the interrupt and call event handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	readl_relaxed(timer->base_addr + TTC_ISR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	ttce->ce.event_handler(&ttce->ce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)  * __ttc_clocksource_read - Reads the timer counter register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)  * returns: Current timer counter register value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)  **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static u64 __ttc_clocksource_read(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	return (u64)readl_relaxed(timer->base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 				TTC_COUNT_VAL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static u64 notrace ttc_sched_clock_read(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	return readl_relaxed(ttc_sched_clock_val_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)  * ttc_set_next_event - Sets the time interval for next event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)  * @cycles:	Timer interval ticks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)  * @evt:	Address of clock event instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)  * returns: Always 0 - success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)  **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static int ttc_set_next_event(unsigned long cycles,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 					struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	struct ttc_timer *timer = &ttce->ttc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	ttc_set_interval(timer, cycles);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)  * ttc_set_{shutdown|oneshot|periodic} - Sets the state of timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)  * @evt:	Address of clock event instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)  **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int ttc_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	struct ttc_timer *timer = &ttce->ttc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	u32 ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int ttc_set_periodic(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	struct ttc_timer *timer = &ttce->ttc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	ttc_set_interval(timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			 DIV_ROUND_CLOSEST(ttce->ttc.freq, PRESCALE * HZ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int ttc_resume(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	struct ttc_timer *timer = &ttce->ttc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	u32 ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		unsigned long event, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	struct clk_notifier_data *ndata = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	struct ttc_timer *ttc = to_ttc_timer(nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	struct ttc_timer_clocksource *ttccs = container_of(ttc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 			struct ttc_timer_clocksource, ttc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	switch (event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	case PRE_RATE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		u32 psv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		unsigned long factor, rate_low, rate_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		if (ndata->new_rate > ndata->old_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			factor = DIV_ROUND_CLOSEST(ndata->new_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 					ndata->old_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			rate_low = ndata->old_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 			rate_high = ndata->new_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 			factor = DIV_ROUND_CLOSEST(ndata->old_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 					ndata->new_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 			rate_low = ndata->new_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 			rate_high = ndata->old_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		if (!is_power_of_2(factor))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 				return NOTIFY_BAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		if (abs(rate_high - (factor * rate_low)) > MAX_F_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 			return NOTIFY_BAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		factor = __ilog2_u32(factor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		 * store timer clock ctrl register so we can restore it in case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		 * of an abort.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		ttccs->scale_clk_ctrl_reg_old =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 			readl_relaxed(ttccs->ttc.base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 			TTC_CLK_CNTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		psv = (ttccs->scale_clk_ctrl_reg_old &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 				TTC_CLK_CNTRL_PSV_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 				TTC_CLK_CNTRL_PSV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		if (ndata->new_rate < ndata->old_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 			psv -= factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 			psv += factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		/* prescaler within legal range? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		if (psv & ~(TTC_CLK_CNTRL_PSV_MASK >> TTC_CLK_CNTRL_PSV_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 			return NOTIFY_BAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		ttccs->scale_clk_ctrl_reg_new = ttccs->scale_clk_ctrl_reg_old &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 			~TTC_CLK_CNTRL_PSV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		ttccs->scale_clk_ctrl_reg_new |= psv << TTC_CLK_CNTRL_PSV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		/* scale down: adjust divider in post-change notification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		if (ndata->new_rate < ndata->old_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 			return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		/* scale up: adjust divider now - before frequency change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 			       ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	case POST_RATE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		/* scale up: pre-change notification did the adjustment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		if (ndata->new_rate > ndata->old_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 			return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		/* scale down: adjust divider now - after frequency change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 			       ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	case ABORT_RATE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		/* we have to undo the adjustment in case we scale up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		if (ndata->new_rate < ndata->old_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 			return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		/* restore original register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		writel_relaxed(ttccs->scale_clk_ctrl_reg_old,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 			       ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int __init ttc_setup_clocksource(struct clk *clk, void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 					 u32 timer_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	struct ttc_timer_clocksource *ttccs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	if (!ttccs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	ttccs->ttc.clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	err = clk_prepare_enable(ttccs->ttc.clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		kfree(ttccs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	ttccs->ttc.freq = clk_get_rate(ttccs->ttc.clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	ttccs->ttc.clk_rate_change_nb.notifier_call =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		ttc_rate_change_clocksource_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	ttccs->ttc.clk_rate_change_nb.next = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	err = clk_notifier_register(ttccs->ttc.clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 				    &ttccs->ttc.clk_rate_change_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		pr_warn("Unable to register clock notifier.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	ttccs->ttc.base_addr = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	ttccs->cs.name = "ttc_clocksource";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	ttccs->cs.rating = 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	ttccs->cs.read = __ttc_clocksource_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	ttccs->cs.mask = CLOCKSOURCE_MASK(timer_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	 * Setup the clock source counter to be an incrementing counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	 * with no interrupt and it rolls over at 0xFFFF. Pre-scale
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	 * it by 32 also. Let it start running now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	writel_relaxed(0x0,  ttccs->ttc.base_addr + TTC_IER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		     ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	writel_relaxed(CNT_CNTRL_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		     ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		kfree(ttccs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	sched_clock_register(ttc_sched_clock_read, timer_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 			     ttccs->ttc.freq / PRESCALE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static int ttc_rate_change_clockevent_cb(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		unsigned long event, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	struct clk_notifier_data *ndata = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	struct ttc_timer *ttc = to_ttc_timer(nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	struct ttc_timer_clockevent *ttcce = container_of(ttc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 			struct ttc_timer_clockevent, ttc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	switch (event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	case POST_RATE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		/* update cached frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		ttc->freq = ndata->new_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		clockevents_update_freq(&ttcce->ce, ndata->new_rate / PRESCALE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	case PRE_RATE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	case ABORT_RATE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static int __init ttc_setup_clockevent(struct clk *clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 				       void __iomem *base, u32 irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	struct ttc_timer_clockevent *ttcce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	if (!ttcce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	ttcce->ttc.clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	err = clk_prepare_enable(ttcce->ttc.clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 		goto out_kfree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	ttcce->ttc.clk_rate_change_nb.notifier_call =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 		ttc_rate_change_clockevent_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	ttcce->ttc.clk_rate_change_nb.next = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	err = clk_notifier_register(ttcce->ttc.clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 				    &ttcce->ttc.clk_rate_change_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 		pr_warn("Unable to register clock notifier.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		goto out_kfree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	ttcce->ttc.freq = clk_get_rate(ttcce->ttc.clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	ttcce->ttc.base_addr = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	ttcce->ce.name = "ttc_clockevent";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	ttcce->ce.set_next_event = ttc_set_next_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	ttcce->ce.set_state_shutdown = ttc_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	ttcce->ce.set_state_periodic = ttc_set_periodic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	ttcce->ce.set_state_oneshot = ttc_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	ttcce->ce.tick_resume = ttc_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	ttcce->ce.rating = 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	ttcce->ce.irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	ttcce->ce.cpumask = cpu_possible_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	 * Setup the clock event timer to be an interval timer which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	 * is prescaled by 32 using the interval interrupt. Leave it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	 * disabled for now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	writel_relaxed(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 		     ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	writel_relaxed(0x1,  ttcce->ttc.base_addr + TTC_IER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	err = request_irq(irq, ttc_clock_event_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 			  IRQF_TIMER, ttcce->ce.name, ttcce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 		goto out_kfree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	clockevents_config_and_register(&ttcce->ce,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 			ttcce->ttc.freq / PRESCALE, 1, 0xfffe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) out_kfree:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	kfree(ttcce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static int __init ttc_timer_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	void __iomem *timer_baseaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	struct clk *clk_cs, *clk_ce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	static int initialized;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	int clksel, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	u32 timer_width = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	struct device_node *timer = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	if (initialized)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	initialized = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	 * Get the 1st Triple Timer Counter (TTC) block from the device tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	 * and use it. Note that the event timer uses the interrupt and it's the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	 * 2nd TTC hence the irq_of_parse_and_map(,1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	timer_baseaddr = of_iomap(timer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	if (!timer_baseaddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 		pr_err("ERROR: invalid timer base address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	irq = irq_of_parse_and_map(timer, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	if (irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 		pr_err("ERROR: invalid interrupt number\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	of_property_read_u32(timer, "timer-width", &timer_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	clk_cs = of_clk_get(timer, clksel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	if (IS_ERR(clk_cs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 		pr_err("ERROR: timer input clock not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 		return PTR_ERR(clk_cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 	clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	clk_ce = of_clk_get(timer, clksel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	if (IS_ERR(clk_ce)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 		pr_err("ERROR: timer input clock not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 		return PTR_ERR(clk_ce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	ret = ttc_setup_clocksource(clk_cs, timer_baseaddr, timer_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 	ret = ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 	pr_info("%pOFn #0 at %p, irq=%d\n", timer, timer_baseaddr, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static const struct of_device_id ttc_timer_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 	{.compatible = "cdns,ttc"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) MODULE_DEVICE_TABLE(of, ttc_timer_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static struct platform_driver ttc_timer_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 		.name	= "cdns_ttc_timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 		.of_match_table = ttc_timer_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) builtin_platform_driver_probe(ttc_timer_driver, ttc_timer_probe);