^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mach-at91/at91rm9200_time.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2003 SAN People
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2003 ATMEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mfd/syscon/atmel-st.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static unsigned long last_crtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static u32 irqmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static struct clock_event_device clkevt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static struct regmap *regmap_st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static int timer_latch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * The ST_CRTR is updated asynchronously to the master clock ... but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * the updates as seen by the CPU don't seem to be strictly monotonic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Waiting until we read the same value twice avoids glitching.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static inline unsigned long read_CRTR(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned int x1, x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) regmap_read(regmap_st, AT91_ST_CRTR, &x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) regmap_read(regmap_st, AT91_ST_CRTR, &x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) if (x1 == x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) x1 = x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * IRQ handler for the timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u32 sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) regmap_read(regmap_st, AT91_ST_SR, &sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) sr &= irqmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * irqs should be disabled here, but as the irq is shared they are only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * guaranteed to be off if the timer irq is registered first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) WARN_ON_ONCE(!irqs_disabled());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* simulate "oneshot" timer with alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (sr & AT91_ST_ALMS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) clkevt.event_handler(&clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* periodic mode should handle delayed ticks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (sr & AT91_ST_PITS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 crtr = read_CRTR();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) while (((crtr - last_crtr) & AT91_ST_CRTV) >= timer_latch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) last_crtr += timer_latch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) clkevt.event_handler(&clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* this irq is shared ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static u64 read_clk32k(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return read_CRTR();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static struct clocksource clk32k = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .name = "32k_counter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .rating = 150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .read = read_clk32k,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .mask = CLOCKSOURCE_MASK(20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .flags = CLOCK_SOURCE_IS_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static void clkdev32k_disable_and_flush_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* Disable and flush pending timer interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) regmap_write(regmap_st, AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) regmap_read(regmap_st, AT91_ST_SR, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) last_crtr = read_CRTR();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int clkevt32k_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) clkdev32k_disable_and_flush_irq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) irqmask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) regmap_write(regmap_st, AT91_ST_IER, irqmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int clkevt32k_set_oneshot(struct clock_event_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) clkdev32k_disable_and_flush_irq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * ALM for oneshot irqs, set by next_event()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * before 32 seconds have passed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) irqmask = AT91_ST_ALMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) regmap_write(regmap_st, AT91_ST_RTAR, last_crtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) regmap_write(regmap_st, AT91_ST_IER, irqmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static int clkevt32k_set_periodic(struct clock_event_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) clkdev32k_disable_and_flush_irq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* PIT for periodic irqs; fixed rate of 1/HZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) irqmask = AT91_ST_PITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) regmap_write(regmap_st, AT91_ST_PIMR, timer_latch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) regmap_write(regmap_st, AT91_ST_IER, irqmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 alm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) BUG_ON(delta < 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* The alarm IRQ uses absolute time (now+delta), not the relative
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * time (delta) in our calling convention. Like all clockevents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * using such "match" hardware, we have a race to defend against.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * Our defense here is to have set up the clockevent device so the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * delta is at least two. That way we never end up writing RTAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * with the value then held in CRTR ... which would mean the match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * wouldn't trigger until 32 seconds later, after CRTR wraps.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) alm = read_CRTR();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Cancel any pending alarm; flush any pending IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) regmap_write(regmap_st, AT91_ST_RTAR, alm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) regmap_read(regmap_st, AT91_ST_SR, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Schedule alarm by writing RTAR. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) alm += delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) regmap_write(regmap_st, AT91_ST_RTAR, alm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static struct clock_event_device clkevt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .name = "at91_tick",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .features = CLOCK_EVT_FEAT_PERIODIC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) CLOCK_EVT_FEAT_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .rating = 150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .set_next_event = clkevt32k_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .set_state_shutdown = clkevt32k_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .set_state_periodic = clkevt32k_set_periodic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .set_state_oneshot = clkevt32k_set_oneshot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .tick_resume = clkevt32k_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * ST (system timer) module supports both clockevents and clocksource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static int __init atmel_st_timer_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct clk *sclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned int sclk_rate, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) regmap_st = syscon_node_to_regmap(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (IS_ERR(regmap_st)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) pr_err("Unable to get regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return PTR_ERR(regmap_st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* Disable all timer interrupts, and clear any pending ones */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) regmap_write(regmap_st, AT91_ST_IDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) regmap_read(regmap_st, AT91_ST_SR, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* Get the interrupts property */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) irq = irq_of_parse_and_map(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (!irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) pr_err("Unable to get IRQ from DT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Make IRQs happen for the system timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ret = request_irq(irq, at91rm9200_timer_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) "at91_tick", regmap_st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) pr_err("Unable to setup IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) sclk = of_clk_get(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (IS_ERR(sclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) pr_err("Unable to get slow clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return PTR_ERR(sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ret = clk_prepare_enable(sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) pr_err("Could not enable slow clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) sclk_rate = clk_get_rate(sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (!sclk_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) pr_err("Invalid slow clock rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) timer_latch = (sclk_rate + HZ / 2) / HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * directly for the clocksource and all clockevents, after adjusting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * its prescaler from the 1 Hz default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) regmap_write(regmap_st, AT91_ST_RTMR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* Setup timer clockevent, with minimum of two ticks (important!!) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) clkevt.cpumask = cpumask_of(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) clockevents_config_and_register(&clkevt, sclk_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 2, AT91_ST_ALMV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* register clocksource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return clocksource_register_hz(&clk32k, sclk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) TIMER_OF_DECLARE(atmel_st_timer, "atmel,at91rm9200-st",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) atmel_st_timer_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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