^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * at91sam926x_time.c - Periodic Interval Timer (PIT) for at91sam926x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Revision 2005 M. Nicolas Diremdjian, ATMEL Rousset, France
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Converted to ClockSource/ClockEvents by David Brownell.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define pr_fmt(fmt) "AT91: PIT: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AT91_PIT_MR 0x00 /* Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AT91_PIT_PITIEN BIT(25) /* Timer Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AT91_PIT_PITEN BIT(24) /* Timer Enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AT91_PIT_PIV GENMASK(19, 0) /* Periodic Interval Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AT91_PIT_SR 0x04 /* Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AT91_PIT_PITS BIT(0) /* Timer Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AT91_PIT_PIVR 0x08 /* Periodic Interval Value Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AT91_PIT_PIIR 0x0c /* Periodic Interval Image Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AT91_PIT_PICNT GENMASK(31, 20) /* Interval Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AT91_PIT_CPIV GENMASK(19, 0) /* Inverval Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PIT_CPIV(x) ((x) & AT91_PIT_CPIV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct pit_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct clock_event_device clkevt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct clocksource clksrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct clk *mck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static inline struct pit_data *clksrc_to_pit_data(struct clocksource *clksrc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return container_of(clksrc, struct pit_data, clksrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static inline struct pit_data *clkevt_to_pit_data(struct clock_event_device *clkevt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return container_of(clkevt, struct pit_data, clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static inline unsigned int pit_read(void __iomem *base, unsigned int reg_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return readl_relaxed(base + reg_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static inline void pit_write(void __iomem *base, unsigned int reg_offset, unsigned long value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) writel_relaxed(value, base + reg_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * Clocksource: just a monotonic counter of MCK/16 cycles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * We don't care whether or not PIT irqs are enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static u64 read_pit_clk(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct pit_data *data = clksrc_to_pit_data(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 elapsed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) raw_local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) elapsed = data->cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) t = pit_read(data->base, AT91_PIT_PIIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) raw_local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) elapsed += PIT_PICNT(t) * data->cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) elapsed += PIT_CPIV(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return elapsed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static int pit_clkevt_shutdown(struct clock_event_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct pit_data *data = clkevt_to_pit_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* disable irq, leaving the clocksource active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) pit_write(data->base, AT91_PIT_MR, (data->cycle - 1) | AT91_PIT_PITEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * Clockevent device: interrupts every 1/HZ (== pit_cycles * MCK/16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int pit_clkevt_set_periodic(struct clock_event_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct pit_data *data = clkevt_to_pit_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* update clocksource counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) data->cnt += data->cycle * PIT_PICNT(pit_read(data->base, AT91_PIT_PIVR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) pit_write(data->base, AT91_PIT_MR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) (data->cycle - 1) | AT91_PIT_PITEN | AT91_PIT_PITIEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static void at91sam926x_pit_suspend(struct clock_event_device *cedev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct pit_data *data = clkevt_to_pit_data(cedev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Disable timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) pit_write(data->base, AT91_PIT_MR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static void at91sam926x_pit_reset(struct pit_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Disable timer and irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) pit_write(data->base, AT91_PIT_MR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Clear any pending interrupts, wait for PIT to stop counting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) while (PIT_CPIV(pit_read(data->base, AT91_PIT_PIVR)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Start PIT but don't enable IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) pit_write(data->base, AT91_PIT_MR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) (data->cycle - 1) | AT91_PIT_PITEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static void at91sam926x_pit_resume(struct clock_event_device *cedev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct pit_data *data = clkevt_to_pit_data(cedev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) at91sam926x_pit_reset(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * IRQ handler for the timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct pit_data *data = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* The PIT interrupt may be disabled, and is shared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (clockevent_state_periodic(&data->clkevt) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) (pit_read(data->base, AT91_PIT_SR) & AT91_PIT_PITS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Get number of ticks performed before irq, and ack it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) data->cnt += data->cycle * PIT_PICNT(pit_read(data->base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) AT91_PIT_PIVR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) data->clkevt.event_handler(&data->clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * Set up both clocksource and clockevent support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int __init at91sam926x_pit_dt_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned long pit_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) unsigned bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct pit_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) data = kzalloc(sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) data->base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (!data->base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) pr_err("Could not map PIT address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) data->mck = of_clk_get(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (IS_ERR(data->mck)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) pr_err("Unable to get mck clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ret = PTR_ERR(data->mck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ret = clk_prepare_enable(data->mck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) pr_err("Unable to enable mck\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Get the interrupts property */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) data->irq = irq_of_parse_and_map(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (!data->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) pr_err("Unable to get IRQ from DT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * Use our actual MCK to figure out how many MCK/16 ticks per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * 1/HZ period (instead of a compile-time constant LATCH).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) pit_rate = clk_get_rate(data->mck) / 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) data->cycle = DIV_ROUND_CLOSEST(pit_rate, HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) WARN_ON(((data->cycle - 1) & ~AT91_PIT_PIV) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Initialize and enable the timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) at91sam926x_pit_reset(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * Register clocksource. The high order bits of PIV are unused,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * so this isn't a 32-bit counter unless we get clockevent irqs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) bits = 12 /* PICNT */ + ilog2(data->cycle) /* PIV */;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) data->clksrc.mask = CLOCKSOURCE_MASK(bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) data->clksrc.name = "pit";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) data->clksrc.rating = 175;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) data->clksrc.read = read_pit_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) data->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ret = clocksource_register_hz(&data->clksrc, pit_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) pr_err("Failed to register clocksource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Set up irq handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ret = request_irq(data->irq, at91sam926x_pit_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) "at91_tick", data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) pr_err("Unable to setup IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) clocksource_unregister(&data->clksrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* Set up and register clockevents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) data->clkevt.name = "pit";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) data->clkevt.features = CLOCK_EVT_FEAT_PERIODIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) data->clkevt.shift = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) data->clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, data->clkevt.shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) data->clkevt.rating = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) data->clkevt.cpumask = cpumask_of(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) data->clkevt.set_state_shutdown = pit_clkevt_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) data->clkevt.set_state_periodic = pit_clkevt_set_periodic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) data->clkevt.resume = at91sam926x_pit_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) data->clkevt.suspend = at91sam926x_pit_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) clockevents_register_device(&data->clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) kfree(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) TIMER_OF_DECLARE(at91sam926x_pit, "atmel,at91sam9260-pit",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) at91sam926x_pit_dt_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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