Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * System timer for CSR SiRFprimaII
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define SIRFSOC_TIMER_32COUNTER_0_CTRL			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define SIRFSOC_TIMER_32COUNTER_1_CTRL			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define SIRFSOC_TIMER_MATCH_0				0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define SIRFSOC_TIMER_MATCH_1				0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define SIRFSOC_TIMER_COUNTER_0				0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define SIRFSOC_TIMER_COUNTER_1				0x004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define SIRFSOC_TIMER_INTR_STATUS			0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define SIRFSOC_TIMER_WATCHDOG_EN			0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define SIRFSOC_TIMER_64COUNTER_CTRL			0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define SIRFSOC_TIMER_64COUNTER_LO			0x006c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define SIRFSOC_TIMER_64COUNTER_HI			0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define SIRFSOC_TIMER_64COUNTER_LOAD_LO			0x0074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SIRFSOC_TIMER_64COUNTER_LOAD_HI			0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define SIRFSOC_TIMER_64COUNTER_RLATCHED_LO		0x007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define SIRFSOC_TIMER_64COUNTER_RLATCHED_HI		0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define SIRFSOC_TIMER_REG_CNT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) static unsigned long atlas7_timer_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	SIRFSOC_TIMER_WATCHDOG_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	SIRFSOC_TIMER_32COUNTER_0_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	SIRFSOC_TIMER_32COUNTER_1_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	SIRFSOC_TIMER_64COUNTER_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	SIRFSOC_TIMER_64COUNTER_RLATCHED_LO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	SIRFSOC_TIMER_64COUNTER_RLATCHED_HI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static void __iomem *sirfsoc_timer_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) /* disable count and interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static inline void sirfsoc_timer_count_disable(int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) /* enable count and interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static inline void sirfsoc_timer_count_enable(int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) /* timer interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	struct clock_event_device *ce = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	/* clear timer interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	writel_relaxed(BIT(cpu), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	if (clockevent_state_oneshot(ce))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		sirfsoc_timer_count_disable(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	ce->event_handler(ce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) /* read 64-bit timer counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) static u64 sirfsoc_timer_read(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	u64 cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			BIT(0)) & ~BIT(1), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	return cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int sirfsoc_timer_set_next_event(unsigned long delta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	struct clock_event_device *ce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	/* disable timer first, then modify the related registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	sirfsoc_timer_count_disable(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		4 * cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		4 * cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	/* enable the tick */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	sirfsoc_timer_count_enable(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Oneshot is enabled in set_next_event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int sirfsoc_timer_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	sirfsoc_timer_count_disable(smp_processor_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static void sirfsoc_clocksource_suspend(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static void sirfsoc_clocksource_resume(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static struct clock_event_device __percpu *sirfsoc_clockevent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static struct clocksource sirfsoc_clocksource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	.name = "sirfsoc_clocksource",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	.rating = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	.mask = CLOCKSOURCE_MASK(64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	.read = sirfsoc_timer_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	.suspend = sirfsoc_clocksource_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	.resume = sirfsoc_clocksource_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static unsigned int sirfsoc_timer_irq, sirfsoc_timer1_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static int sirfsoc_local_timer_starting_cpu(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	struct clock_event_device *ce = per_cpu_ptr(sirfsoc_clockevent, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	if (cpu == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		irq = sirfsoc_timer_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		name = "sirfsoc_timer0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		irq = sirfsoc_timer1_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		name = "sirfsoc_timer1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	ce->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	ce->name = "local_timer";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	ce->features = CLOCK_EVT_FEAT_ONESHOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	ce->rating = 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	ce->set_state_shutdown = sirfsoc_timer_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	ce->set_state_oneshot = sirfsoc_timer_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	ce->tick_resume = sirfsoc_timer_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	ce->set_next_event = sirfsoc_timer_set_next_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	clockevents_calc_mult_shift(ce, atlas7_timer_rate, 60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	ce->max_delta_ns = clockevent_delta2ns(-2, ce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	ce->max_delta_ticks = (unsigned long)-2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	ce->min_delta_ns = clockevent_delta2ns(2, ce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	ce->min_delta_ticks = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	ce->cpumask = cpumask_of(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	BUG_ON(request_irq(ce->irq, sirfsoc_timer_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			   IRQF_TIMER | IRQF_NOBALANCING, name, ce));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	irq_force_affinity(ce->irq, cpumask_of(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	clockevents_register_device(ce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static int sirfsoc_local_timer_dying_cpu(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	struct clock_event_device *ce = per_cpu_ptr(sirfsoc_clockevent, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	sirfsoc_timer_count_disable(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	if (cpu == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		free_irq(sirfsoc_timer_irq, ce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		free_irq(sirfsoc_timer1_irq, ce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int __init sirfsoc_clockevent_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	sirfsoc_clockevent = alloc_percpu(struct clock_event_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	BUG_ON(!sirfsoc_clockevent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	/* Install and invoke hotplug callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	return cpuhp_setup_state(CPUHP_AP_MARCO_TIMER_STARTING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 				 "clockevents/marco:starting",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 				 sirfsoc_local_timer_starting_cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 				 sirfsoc_local_timer_dying_cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* initialize the kernel jiffy timer source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int __init sirfsoc_atlas7_timer_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	clk = of_clk_get(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	BUG_ON(IS_ERR(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	BUG_ON(clk_prepare_enable(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	atlas7_timer_rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	/* timer dividers: 0, not divided */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_1_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	/* Initialize timer counters to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	/* Clear all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, atlas7_timer_rate));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	return sirfsoc_clockevent_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static int __init sirfsoc_of_timer_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	sirfsoc_timer_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	if (!sirfsoc_timer_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		pr_err("unable to map timer cpu registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	sirfsoc_timer_irq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	if (!sirfsoc_timer_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		pr_err("No irq passed for timer0 via DT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	sirfsoc_timer1_irq = irq_of_parse_and_map(np, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	if (!sirfsoc_timer1_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		pr_err("No irq passed for timer1 via DT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	return sirfsoc_atlas7_timer_init(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) TIMER_OF_DECLARE(sirfsoc_atlas7_timer, "sirf,atlas7-tick", sirfsoc_of_timer_init);