^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Marvell Armada 370/XP SoC timer handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2012 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Lior Amsalem <alior@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Gregory CLEMENT <gregory.clement@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Timer 0 is used as free-running clocksource, while timer 1 is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * used as clock_event_device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Clocksource driver for Armada 370 and Armada XP SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * This driver implements one compatible string for each SoC, given
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * each has its own characteristics:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * * Armada 370 has no 25 MHz fixed timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * * Armada XP cannot work properly without such 25 MHz fixed timer as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * doing otherwise leads to using a clocksource whose frequency varies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * when doing cpufreq frequency changes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * See Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/percpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <asm/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * Timer block registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TIMER_CTRL_OFF 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TIMER0_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TIMER0_RELOAD_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TIMER0_25MHZ BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TIMER0_DIV(div) ((div) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TIMER1_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TIMER1_RELOAD_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TIMER1_25MHZ BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TIMER1_DIV(div) ((div) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TIMER_EVENTS_STATUS 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TIMER0_CLR_MASK (~0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TIMER1_CLR_MASK (~0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TIMER0_RELOAD_OFF 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TIMER0_VAL_OFF 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TIMER1_RELOAD_OFF 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TIMER1_VAL_OFF 0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define LCL_TIMER_EVENTS_STATUS 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Global timers are connected to the coherency fabric clock, and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) below divider reduces their incrementing frequency. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TIMER_DIVIDER_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define TIMER_DIVIDER (1 << TIMER_DIVIDER_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * SoC-specific data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static void __iomem *timer_base, *local_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static unsigned int timer_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static bool timer25Mhz = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static u32 enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * Number of timer ticks per jiffy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static u32 ticks_per_jiffy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static struct clock_event_device __percpu *armada_370_xp_evt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static void local_timer_ctrl_clrset(u32 clr, u32 set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) local_base + TIMER_CTRL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static u64 notrace armada_370_xp_read_sched_clock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return ~readl(timer_base + TIMER0_VAL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * Clockevent handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) armada_370_xp_clkevt_next_event(unsigned long delta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct clock_event_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * Clear clockevent timer interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * Setup new clockevent timer value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) writel(delta, local_base + TIMER0_VAL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * Enable the timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) local_timer_ctrl_clrset(TIMER0_RELOAD_EN, enable_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int armada_370_xp_clkevt_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * Disable timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) local_timer_ctrl_clrset(TIMER0_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * ACK pending timer interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int armada_370_xp_clkevt_set_periodic(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * Setup timer to fire at 1/HZ intervals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) writel(ticks_per_jiffy - 1, local_base + TIMER0_RELOAD_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) writel(ticks_per_jiffy - 1, local_base + TIMER0_VAL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * Enable timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) local_timer_ctrl_clrset(0, TIMER0_RELOAD_EN | enable_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int armada_370_xp_clkevt_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static irqreturn_t armada_370_xp_timer_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * ACK timer interrupt and call event handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct clock_event_device *evt = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) evt->event_handler(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * Setup the local clock events for a CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static int armada_370_xp_timer_starting_cpu(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct clock_event_device *evt = per_cpu_ptr(armada_370_xp_evt, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 clr = 0, set = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (timer25Mhz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) set = TIMER0_25MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) clr = TIMER0_25MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) local_timer_ctrl_clrset(clr, set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) evt->name = "armada_370_xp_per_cpu_tick";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) evt->features = CLOCK_EVT_FEAT_ONESHOT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) CLOCK_EVT_FEAT_PERIODIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) evt->shift = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) evt->rating = 300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) evt->set_next_event = armada_370_xp_clkevt_next_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) evt->set_state_shutdown = armada_370_xp_clkevt_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) evt->set_state_periodic = armada_370_xp_clkevt_set_periodic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) evt->set_state_oneshot = armada_370_xp_clkevt_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) evt->tick_resume = armada_370_xp_clkevt_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) evt->irq = armada_370_xp_clkevt_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) evt->cpumask = cpumask_of(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) clockevents_config_and_register(evt, timer_clk, 1, 0xfffffffe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) enable_percpu_irq(evt->irq, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int armada_370_xp_timer_dying_cpu(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct clock_event_device *evt = per_cpu_ptr(armada_370_xp_evt, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) evt->set_state_shutdown(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) disable_percpu_irq(evt->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static u32 timer0_ctrl_reg, timer0_local_ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int armada_370_xp_timer_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) timer0_ctrl_reg = readl(timer_base + TIMER_CTRL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) timer0_local_ctrl_reg = readl(local_base + TIMER_CTRL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static void armada_370_xp_timer_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) writel(timer0_ctrl_reg, timer_base + TIMER_CTRL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) writel(timer0_local_ctrl_reg, local_base + TIMER_CTRL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static struct syscore_ops armada_370_xp_timer_syscore_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .suspend = armada_370_xp_timer_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .resume = armada_370_xp_timer_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static unsigned long armada_370_delay_timer_read(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return ~readl(timer_base + TIMER0_VAL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static struct delay_timer armada_370_delay_timer = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .read_current_timer = armada_370_delay_timer_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int __init armada_370_xp_timer_common_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u32 clr = 0, set = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) timer_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (!timer_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) pr_err("Failed to iomap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) local_base = of_iomap(np, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (!local_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) pr_err("Failed to iomap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (timer25Mhz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) set = TIMER0_25MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) enable_mask = TIMER0_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) clr = TIMER0_25MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) enable_mask = TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) atomic_io_modify(timer_base + TIMER_CTRL_OFF, clr | set, set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) local_timer_ctrl_clrset(clr, set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * We use timer 0 as clocksource, and private(local) timer 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * for clockevents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) armada_370_xp_clkevt_irq = irq_of_parse_and_map(np, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) ticks_per_jiffy = (timer_clk + HZ / 2) / HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * Setup free-running clocksource timer (interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * disabled).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) atomic_io_modify(timer_base + TIMER_CTRL_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) TIMER0_RELOAD_EN | enable_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) TIMER0_RELOAD_EN | enable_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) armada_370_delay_timer.freq = timer_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) register_current_timer_delay(&armada_370_delay_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * Set scale and timer for sched_clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) sched_clock_register(armada_370_xp_read_sched_clock, 32, timer_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) res = clocksource_mmio_init(timer_base + TIMER0_VAL_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) "armada_370_xp_clocksource",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) timer_clk, 300, 32, clocksource_mmio_readl_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) pr_err("Failed to initialize clocksource mmio\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) armada_370_xp_evt = alloc_percpu(struct clock_event_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (!armada_370_xp_evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * Setup clockevent timer (interrupt-driven).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) res = request_percpu_irq(armada_370_xp_clkevt_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) armada_370_xp_timer_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) "armada_370_xp_per_cpu_tick",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) armada_370_xp_evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* Immediately configure the timer on the boot CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) pr_err("Failed to request percpu irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) res = cpuhp_setup_state(CPUHP_AP_ARMADA_TIMER_STARTING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) "clockevents/armada:starting",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) armada_370_xp_timer_starting_cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) armada_370_xp_timer_dying_cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) pr_err("Failed to setup hotplug state and timer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) register_syscore_ops(&armada_370_xp_timer_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int __init armada_xp_timer_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct clk *clk = of_clk_get_by_name(np, "fixed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) pr_err("Failed to get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) timer_clk = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return armada_370_xp_timer_common_init(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) TIMER_OF_DECLARE(armada_xp, "marvell,armada-xp-timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) armada_xp_timer_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static int __init armada_375_timer_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) clk = of_clk_get_by_name(np, "fixed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (!IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) timer_clk = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * This fallback is required in order to retain proper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * devicetree backwards compatibility.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) clk = of_clk_get(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* Must have at least a clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) pr_err("Failed to get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) timer_clk = clk_get_rate(clk) / TIMER_DIVIDER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) timer25Mhz = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return armada_370_xp_timer_common_init(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) TIMER_OF_DECLARE(armada_375, "marvell,armada-375-timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) armada_375_timer_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static int __init armada_370_timer_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) clk = of_clk_get(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) pr_err("Failed to get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) timer_clk = clk_get_rate(clk) / TIMER_DIVIDER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) timer25Mhz = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return armada_370_xp_timer_common_init(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) TIMER_OF_DECLARE(armada_370, "marvell,armada-370-timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) armada_370_timer_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags