^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SuperH Timer Support - TMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009 Magnus Damm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pm_domain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/sh_timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #ifdef CONFIG_SUPERH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/platform_early.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) enum sh_tmu_model {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) SH_TMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) SH_TMU_SH3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct sh_tmu_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct sh_tmu_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct sh_tmu_device *tmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned long periodic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct clock_event_device ced;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct clocksource cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) bool cs_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned int enable_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct sh_tmu_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) void __iomem *mapbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) enum sh_tmu_model model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) raw_spinlock_t lock; /* Protect the shared start/stop register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct sh_tmu_channel *channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned int num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) bool has_clockevent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) bool has_clocksource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TSTR -1 /* shared register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TCOR 0 /* channel register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TCNT 1 /* channel register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TCR 2 /* channel register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define TCR_UNF (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define TCR_UNIE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define TCR_TPSC_CLK4 (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define TCR_TPSC_CLK16 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define TCR_TPSC_CLK64 (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define TCR_TPSC_CLK256 (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TCR_TPSC_CLK1024 (4 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define TCR_TPSC_MASK (7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) unsigned long offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (reg_nr == TSTR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) switch (ch->tmu->model) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) case SH_TMU_SH3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return ioread8(ch->tmu->mapbase + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) case SH_TMU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return ioread8(ch->tmu->mapbase + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) offs = reg_nr << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (reg_nr == TCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return ioread16(ch->base + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return ioread32(ch->base + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static inline void sh_tmu_write(struct sh_tmu_channel *ch, int reg_nr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned long value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned long offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (reg_nr == TSTR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) switch (ch->tmu->model) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) case SH_TMU_SH3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return iowrite8(value, ch->tmu->mapbase + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) case SH_TMU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return iowrite8(value, ch->tmu->mapbase + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) offs = reg_nr << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (reg_nr == TCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) iowrite16(value, ch->base + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) iowrite32(value, ch->base + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void sh_tmu_start_stop_ch(struct sh_tmu_channel *ch, int start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned long flags, value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* start stop register shared by multiple timer channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) raw_spin_lock_irqsave(&ch->tmu->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) value = sh_tmu_read(ch, TSTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) value |= 1 << ch->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) value &= ~(1 << ch->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) sh_tmu_write(ch, TSTR, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) raw_spin_unlock_irqrestore(&ch->tmu->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int __sh_tmu_enable(struct sh_tmu_channel *ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* enable clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ret = clk_enable(ch->tmu->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) dev_err(&ch->tmu->pdev->dev, "ch%u: cannot enable clock\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ch->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* make sure channel is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) sh_tmu_start_stop_ch(ch, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* maximum timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) sh_tmu_write(ch, TCOR, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) sh_tmu_write(ch, TCNT, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* configure channel to parent clock / 4, irq off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* enable channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) sh_tmu_start_stop_ch(ch, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int sh_tmu_enable(struct sh_tmu_channel *ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (ch->enable_count++ > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) pm_runtime_get_sync(&ch->tmu->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) dev_pm_syscore_device(&ch->tmu->pdev->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return __sh_tmu_enable(ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static void __sh_tmu_disable(struct sh_tmu_channel *ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* disable channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) sh_tmu_start_stop_ch(ch, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* disable interrupts in TMU block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* stop clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) clk_disable(ch->tmu->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static void sh_tmu_disable(struct sh_tmu_channel *ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (WARN_ON(ch->enable_count == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (--ch->enable_count > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) __sh_tmu_disable(ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) dev_pm_syscore_device(&ch->tmu->pdev->dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) pm_runtime_put(&ch->tmu->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int periodic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* stop timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) sh_tmu_start_stop_ch(ch, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* acknowledge interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) sh_tmu_read(ch, TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* enable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* reload delta value in case of periodic timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (periodic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) sh_tmu_write(ch, TCOR, delta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) sh_tmu_write(ch, TCOR, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) sh_tmu_write(ch, TCNT, delta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* start timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) sh_tmu_start_stop_ch(ch, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct sh_tmu_channel *ch = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* disable or acknowledge interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (clockevent_state_oneshot(&ch->ced))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* notify clockevent layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ch->ced.event_handler(&ch->ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static struct sh_tmu_channel *cs_to_sh_tmu(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return container_of(cs, struct sh_tmu_channel, cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static u64 sh_tmu_clocksource_read(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return sh_tmu_read(ch, TCNT) ^ 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static int sh_tmu_clocksource_enable(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (WARN_ON(ch->cs_enabled))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ret = sh_tmu_enable(ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ch->cs_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static void sh_tmu_clocksource_disable(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (WARN_ON(!ch->cs_enabled))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) sh_tmu_disable(ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ch->cs_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static void sh_tmu_clocksource_suspend(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (!ch->cs_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (--ch->enable_count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) __sh_tmu_disable(ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dev_pm_genpd_suspend(&ch->tmu->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static void sh_tmu_clocksource_resume(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (!ch->cs_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (ch->enable_count++ == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) dev_pm_genpd_resume(&ch->tmu->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) __sh_tmu_enable(ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static int sh_tmu_register_clocksource(struct sh_tmu_channel *ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct clocksource *cs = &ch->cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) cs->name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) cs->rating = 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) cs->read = sh_tmu_clocksource_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) cs->enable = sh_tmu_clocksource_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) cs->disable = sh_tmu_clocksource_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) cs->suspend = sh_tmu_clocksource_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) cs->resume = sh_tmu_clocksource_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) cs->mask = CLOCKSOURCE_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) dev_info(&ch->tmu->pdev->dev, "ch%u: used as clock source\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ch->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) clocksource_register_hz(cs, ch->tmu->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static struct sh_tmu_channel *ced_to_sh_tmu(struct clock_event_device *ced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return container_of(ced, struct sh_tmu_channel, ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static void sh_tmu_clock_event_start(struct sh_tmu_channel *ch, int periodic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) sh_tmu_enable(ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (periodic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ch->periodic = (ch->tmu->rate + HZ/2) / HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) sh_tmu_set_next(ch, ch->periodic, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int sh_tmu_clock_event_shutdown(struct clock_event_device *ced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) sh_tmu_disable(ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static int sh_tmu_clock_event_set_state(struct clock_event_device *ced,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int periodic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* deal with old setting first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) sh_tmu_disable(ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) dev_info(&ch->tmu->pdev->dev, "ch%u: used for %s clock events\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ch->index, periodic ? "periodic" : "oneshot");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) sh_tmu_clock_event_start(ch, periodic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static int sh_tmu_clock_event_set_oneshot(struct clock_event_device *ced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return sh_tmu_clock_event_set_state(ced, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static int sh_tmu_clock_event_set_periodic(struct clock_event_device *ced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return sh_tmu_clock_event_set_state(ced, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static int sh_tmu_clock_event_next(unsigned long delta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct clock_event_device *ced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) BUG_ON(!clockevent_state_oneshot(ced));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* program new delta value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) sh_tmu_set_next(ch, delta, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static void sh_tmu_clock_event_suspend(struct clock_event_device *ced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) dev_pm_genpd_suspend(&ced_to_sh_tmu(ced)->tmu->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static void sh_tmu_clock_event_resume(struct clock_event_device *ced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) dev_pm_genpd_resume(&ced_to_sh_tmu(ced)->tmu->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct clock_event_device *ced = &ch->ced;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ced->name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ced->features = CLOCK_EVT_FEAT_PERIODIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) ced->features |= CLOCK_EVT_FEAT_ONESHOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ced->rating = 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ced->cpumask = cpu_possible_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ced->set_next_event = sh_tmu_clock_event_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ced->set_state_shutdown = sh_tmu_clock_event_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ced->set_state_periodic = sh_tmu_clock_event_set_periodic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ced->set_state_oneshot = sh_tmu_clock_event_set_oneshot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ced->suspend = sh_tmu_clock_event_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) ced->resume = sh_tmu_clock_event_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) dev_info(&ch->tmu->pdev->dev, "ch%u: used for clock events\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ch->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) clockevents_config_and_register(ced, ch->tmu->rate, 0x300, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ret = request_irq(ch->irq, sh_tmu_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) dev_name(&ch->tmu->pdev->dev), ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) dev_err(&ch->tmu->pdev->dev, "ch%u: failed to request irq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ch->index, ch->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static int sh_tmu_register(struct sh_tmu_channel *ch, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) bool clockevent, bool clocksource)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (clockevent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ch->tmu->has_clockevent = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) sh_tmu_register_clockevent(ch, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) } else if (clocksource) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) ch->tmu->has_clocksource = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) sh_tmu_register_clocksource(ch, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) bool clockevent, bool clocksource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct sh_tmu_device *tmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* Skip unused channels. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (!clockevent && !clocksource)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) ch->tmu = tmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ch->index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (tmu->model == SH_TMU_SH3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ch->base = tmu->mapbase + 4 + ch->index * 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ch->base = tmu->mapbase + 8 + ch->index * 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ch->irq = platform_get_irq(tmu->pdev, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (ch->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return ch->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) ch->cs_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ch->enable_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return sh_tmu_register(ch, dev_name(&tmu->pdev->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) clockevent, clocksource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static int sh_tmu_map_memory(struct sh_tmu_device *tmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) res = platform_get_resource(tmu->pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) dev_err(&tmu->pdev->dev, "failed to get I/O memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) tmu->mapbase = ioremap(res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (tmu->mapbase == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static int sh_tmu_parse_dt(struct sh_tmu_device *tmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct device_node *np = tmu->pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) tmu->model = SH_TMU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) tmu->num_channels = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) of_property_read_u32(np, "#renesas,channels", &tmu->num_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (tmu->num_channels != 2 && tmu->num_channels != 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) dev_err(&tmu->pdev->dev, "invalid number of channels %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) tmu->num_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) tmu->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) raw_spin_lock_init(&tmu->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ret = sh_tmu_parse_dt(tmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) } else if (pdev->dev.platform_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) const struct platform_device_id *id = pdev->id_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct sh_timer_config *cfg = pdev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) tmu->model = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) tmu->num_channels = hweight8(cfg->channels_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) dev_err(&tmu->pdev->dev, "missing platform data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* Get hold of clock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) tmu->clk = clk_get(&tmu->pdev->dev, "fck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (IS_ERR(tmu->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) dev_err(&tmu->pdev->dev, "cannot get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return PTR_ERR(tmu->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) ret = clk_prepare(tmu->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) goto err_clk_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /* Determine clock rate. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) ret = clk_enable(tmu->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) goto err_clk_unprepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) tmu->rate = clk_get_rate(tmu->clk) / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) clk_disable(tmu->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* Map the memory resource. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ret = sh_tmu_map_memory(tmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) dev_err(&tmu->pdev->dev, "failed to remap I/O memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) goto err_clk_unprepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* Allocate and setup the channels. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) tmu->channels = kcalloc(tmu->num_channels, sizeof(*tmu->channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (tmu->channels == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) goto err_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * Use the first channel as a clock event device and the second channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * as a clock source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) for (i = 0; i < tmu->num_channels; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ret = sh_tmu_channel_setup(&tmu->channels[i], i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) i == 0, i == 1, tmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) goto err_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) platform_set_drvdata(pdev, tmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) err_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) kfree(tmu->channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) iounmap(tmu->mapbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) err_clk_unprepare:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) clk_unprepare(tmu->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) err_clk_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) clk_put(tmu->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static int sh_tmu_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct sh_tmu_device *tmu = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (!is_sh_early_platform_device(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) pm_runtime_set_active(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (tmu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) dev_info(&pdev->dev, "kept as earlytimer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) tmu = kzalloc(sizeof(*tmu), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (tmu == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) ret = sh_tmu_setup(tmu, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) kfree(tmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) pm_runtime_idle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (is_sh_early_platform_device(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (tmu->has_clockevent || tmu->has_clocksource)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) pm_runtime_irq_safe(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) pm_runtime_idle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static int sh_tmu_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return -EBUSY; /* cannot unregister clockevent and clocksource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static const struct platform_device_id sh_tmu_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) { "sh-tmu", SH_TMU },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) { "sh-tmu-sh3", SH_TMU_SH3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) MODULE_DEVICE_TABLE(platform, sh_tmu_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static const struct of_device_id sh_tmu_of_table[] __maybe_unused = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) { .compatible = "renesas,tmu" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) MODULE_DEVICE_TABLE(of, sh_tmu_of_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static struct platform_driver sh_tmu_device_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .probe = sh_tmu_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .remove = sh_tmu_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .name = "sh_tmu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .of_match_table = of_match_ptr(sh_tmu_of_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .id_table = sh_tmu_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static int __init sh_tmu_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) return platform_driver_register(&sh_tmu_device_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static void __exit sh_tmu_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) platform_driver_unregister(&sh_tmu_device_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #ifdef CONFIG_SUPERH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) sh_early_platform_init("earlytimer", &sh_tmu_device_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) subsys_initcall(sh_tmu_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) module_exit(sh_tmu_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) MODULE_AUTHOR("Magnus Damm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) MODULE_DESCRIPTION("SuperH TMU Timer Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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