^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2006 Jim Cromie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This is a clocksource driver for the Geode SCx200's 1 or 27 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * high-resolution timer. The Geode SC-1100 (at least) has a buggy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * time stamp counter (TSC), which loses time unless 'idle=poll' is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * given as a boot-arg. In its absence, the Generic Timekeeping code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * will detect and de-rate the bad TSC, allowing this timer to take
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * over timekeeping duties.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Based on work by John Stultz, and Ted Phelps (in a 2.6.12-rc6 patch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/scx200.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define NAME "scx200_hrt"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static int mhz27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) module_param(mhz27, int, 0); /* load time only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) MODULE_PARM_DESC(mhz27, "count at 27.0 MHz (default is 1.0 MHz)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static int ppm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) module_param(ppm, int, 0); /* load time only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MODULE_PARM_DESC(ppm, "+-adjust to actual XO freq (ppm)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* HiRes Timer configuration register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SCx200_TMCNFG_OFFSET (SCx200_TIMER_OFFSET + 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* and config settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define HR_TMEN (1 << 0) /* timer interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define HR_TMCLKSEL (1 << 1) /* 1|0 counts at 27|1 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define HR_TM27MPD (1 << 2) /* 1 turns off input clock (power-down) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* The base timer frequency, * 27 if selected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define HRT_FREQ 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static u64 read_hrt(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Read the timer value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return (u64) inl(scx200_cb_base + SCx200_TIMER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static struct clocksource cs_hrt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .name = "scx200_hrt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .rating = 250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .read = read_hrt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .mask = CLOCKSOURCE_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .flags = CLOCK_SOURCE_IS_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* mult, shift are set based on mhz27 flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static int __init init_hrt_clocksource(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Make sure scx200 has initialized the configuration block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (!scx200_cb_present())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Reserve the timer's ISA io-region for ourselves */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (!request_region(scx200_cb_base + SCx200_TIMER_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) SCx200_TIMER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) "NatSemi SCx200 High-Resolution Timer")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) pr_warn("unable to lock timer region\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* write timer config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) outb(HR_TMEN | (mhz27 ? HR_TMCLKSEL : 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) scx200_cb_base + SCx200_TMCNFG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) freq = (HRT_FREQ + ppm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (mhz27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) freq *= 27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) pr_info("enabling scx200 high-res timer (%s MHz +%d ppm)\n", mhz27 ? "27":"1", ppm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return clocksource_register_hz(&cs_hrt, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) module_init(init_hrt_clocksource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MODULE_AUTHOR("Jim Cromie <jim.cromie@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MODULE_DESCRIPTION("clocksource on SCx200 HiRes Timer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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