^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Renesas Timer Support - OSTM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Renesas Electronics America, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2017 Chris Brandt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "timer-of.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * The OSTM contains independent channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * The first OSTM channel probed will be set up as a free running
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * clocksource. Additionally we will use this clocksource for the system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * schedule timer sched_clock().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * The second (or more) channel probed will be set up as an interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * driven clock event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static void __iomem *system_clock; /* For sched_clock() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* OSTM REGISTERS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define OSTM_CMP 0x000 /* RW,32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OSTM_CNT 0x004 /* R,32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OSTM_TE 0x010 /* R,8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OSTM_TS 0x014 /* W,8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OSTM_TT 0x018 /* W,8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OSTM_CTL 0x020 /* RW,8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CTL_PERIODIC 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CTL_ONESHOT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CTL_FREERUN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static void ostm_timer_stop(struct timer_of *to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) if (readb(timer_of_base(to) + OSTM_TE) & TE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) writeb(TT, timer_of_base(to) + OSTM_TT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Read back the register simply to confirm the write operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * has completed since I/O writes can sometimes get queued by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * the bus architecture.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) while (readb(timer_of_base(to) + OSTM_TE) & TE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static int __init ostm_init_clksrc(struct timer_of *to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ostm_timer_stop(to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) writel(0, timer_of_base(to) + OSTM_CMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) writeb(CTL_FREERUN, timer_of_base(to) + OSTM_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) writeb(TS, timer_of_base(to) + OSTM_TS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return clocksource_mmio_init(timer_of_base(to) + OSTM_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) to->np->full_name, timer_of_rate(to), 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 32, clocksource_mmio_readl_up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static u64 notrace ostm_read_sched_clock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return readl(system_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static void __init ostm_init_sched_clock(struct timer_of *to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) system_clock = timer_of_base(to) + OSTM_CNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) sched_clock_register(ostm_read_sched_clock, 32, timer_of_rate(to));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static int ostm_clock_event_next(unsigned long delta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct clock_event_device *ced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct timer_of *to = to_timer_of(ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ostm_timer_stop(to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) writel(delta, timer_of_base(to) + OSTM_CMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) writeb(CTL_ONESHOT, timer_of_base(to) + OSTM_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) writeb(TS, timer_of_base(to) + OSTM_TS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static int ostm_shutdown(struct clock_event_device *ced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct timer_of *to = to_timer_of(ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ostm_timer_stop(to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int ostm_set_periodic(struct clock_event_device *ced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct timer_of *to = to_timer_of(ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ostm_timer_stop(to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) writel(timer_of_period(to) - 1, timer_of_base(to) + OSTM_CMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) writeb(CTL_PERIODIC, timer_of_base(to) + OSTM_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) writeb(TS, timer_of_base(to) + OSTM_TS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int ostm_set_oneshot(struct clock_event_device *ced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct timer_of *to = to_timer_of(ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ostm_timer_stop(to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static irqreturn_t ostm_timer_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct clock_event_device *ced = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (clockevent_state_oneshot(ced))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ostm_timer_stop(to_timer_of(ced));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* notify clockevent layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (ced->event_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ced->event_handler(ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int __init ostm_init_clkevt(struct timer_of *to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct clock_event_device *ced = &to->clkevt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ced->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ced->set_state_shutdown = ostm_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ced->set_state_periodic = ostm_set_periodic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ced->set_state_oneshot = ostm_set_oneshot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ced->set_next_event = ostm_clock_event_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ced->shift = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ced->rating = 300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ced->cpumask = cpumask_of(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) clockevents_config_and_register(ced, timer_of_rate(to), 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static int __init ostm_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct timer_of *to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) to = kzalloc(sizeof(*to), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (!to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) to->flags = TIMER_OF_BASE | TIMER_OF_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (system_clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * clock sources don't use interrupts, clock events do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) to->flags |= TIMER_OF_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) to->of_irq.flags = IRQF_TIMER | IRQF_IRQPOLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) to->of_irq.handler = ostm_timer_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ret = timer_of_init(np, to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * First probed device will be used as system clocksource. Any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * additional devices will be used as clock events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (!system_clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ret = ostm_init_clksrc(to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) goto err_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ostm_init_sched_clock(to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) pr_info("%pOF: used for clocksource\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ret = ostm_init_clkevt(to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) goto err_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) pr_info("%pOF: used for clock events\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) err_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) timer_of_cleanup(to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) err_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) kfree(to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) TIMER_OF_DECLARE(ostm, "renesas,ostm", ostm_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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