^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2015 Numascale AS. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/numachip/numachip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/numachip/numachip_csr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) static DEFINE_PER_CPU(struct clock_event_device, numachip2_ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static cycles_t numachip2_timer_read(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) return numachip2_read64_lcsr(NUMACHIP2_TIMER_NOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static struct clocksource numachip2_clocksource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) .name = "numachip2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) .rating = 295,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .read = numachip2_timer_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .mask = CLOCKSOURCE_MASK(64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) .flags = CLOCK_SOURCE_IS_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static int numachip2_set_next_event(unsigned long delta, struct clock_event_device *ced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) numachip2_write64_lcsr(NUMACHIP2_TIMER_DEADLINE + numachip2_timer(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) delta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static const struct clock_event_device numachip2_clockevent __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .name = "numachip2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .rating = 400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .set_next_event = numachip2_set_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .features = CLOCK_EVT_FEAT_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .min_delta_ns = 1250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .min_delta_ticks = 1250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .max_delta_ns = LONG_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .max_delta_ticks = LONG_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static void numachip_timer_interrupt(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct clock_event_device *ced = this_cpu_ptr(&numachip2_ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ced->event_handler(ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static __init void numachip_timer_each(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned local_apicid = __this_cpu_read(x86_cpu_to_apicid) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct clock_event_device *ced = this_cpu_ptr(&numachip2_ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Setup IPI vector to local core and relative timing mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) numachip2_write64_lcsr(NUMACHIP2_TIMER_INT + numachip2_timer(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) (3 << 22) | (X86_PLATFORM_IPI_VECTOR << 14) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) (local_apicid << 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) *ced = numachip2_clockevent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ced->cpumask = cpumask_of(smp_processor_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) clockevents_register_device(ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static int __init numachip_timer_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (numachip_system != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Reset timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) numachip2_write64_lcsr(NUMACHIP2_TIMER_RESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) clocksource_register_hz(&numachip2_clocksource, NSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Setup per-cpu clockevents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) x86_platform_ipi_callback = numachip_timer_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) schedule_on_each_cpu(&numachip_timer_each);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) arch_initcall(numachip_timer_init);