^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2008 STMicroelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2010 Alessandro Rubini
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010 Linus Walleij for ST-Ericsson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/mach/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * The MTU device hosts four different counters, with 4 set of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * registers. These are register names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MTU_IMSC 0x00 /* Interrupt mask set/clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MTU_RIS 0x04 /* Raw interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MTU_MIS 0x08 /* Masked interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MTU_ICR 0x0C /* Interrupt clear register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* per-timer registers take 0..3 as argument */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* bits for the control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MTU_CRn_ENA 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MTU_CRn_PRESCALE_MASK 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MTU_CRn_PRESCALE_1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MTU_CRn_PRESCALE_16 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MTU_CRn_PRESCALE_256 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MTU_CRn_32BITS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Other registers are usual amba/primecell registers, currently not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MTU_ITCR 0xff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MTU_ITOP 0xff4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MTU_PERIPH_ID0 0xfe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MTU_PERIPH_ID1 0xfe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MTU_PERIPH_ID2 0xfe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MTU_PERIPH_ID3 0xfeC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MTU_PCELL0 0xff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MTU_PCELL1 0xff4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MTU_PCELL2 0xff8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MTU_PCELL3 0xffC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static void __iomem *mtu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static bool clkevt_periodic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static u32 clk_prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static u32 nmdk_cycle; /* write-once */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static struct delay_timer mtu_delay_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * Override the global weak sched_clock symbol with this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * local implementation which uses the clocksource to get some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * better resolution when scheduling the kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static u64 notrace nomadik_read_sched_clock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (unlikely(!mtu_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return -readl(mtu_base + MTU_VAL(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static unsigned long nmdk_timer_read_current_timer(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return ~readl_relaxed(mtu_base + MTU_VAL(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Clockevent device: use one-shot mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) writel(1 << 1, mtu_base + MTU_IMSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) writel(evt, mtu_base + MTU_LR(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Load highest value, enable device, enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) writel(MTU_CRn_ONESHOT | clk_prescale |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MTU_CRn_32BITS | MTU_CRn_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) mtu_base + MTU_CR(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static void nmdk_clkevt_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (clkevt_periodic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Timer: configure load and background-load, and fire it up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) writel(nmdk_cycle, mtu_base + MTU_LR(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) writel(nmdk_cycle, mtu_base + MTU_BGLR(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) writel(MTU_CRn_PERIODIC | clk_prescale |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MTU_CRn_32BITS | MTU_CRn_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) mtu_base + MTU_CR(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) writel(1 << 1, mtu_base + MTU_IMSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Generate an interrupt to start the clockevent again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) (void) nmdk_clkevt_next(nmdk_cycle, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int nmdk_clkevt_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) writel(0, mtu_base + MTU_IMSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* disable timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) writel(0, mtu_base + MTU_CR(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* load some high default value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) writel(0xffffffff, mtu_base + MTU_LR(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static int nmdk_clkevt_set_oneshot(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) clkevt_periodic = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int nmdk_clkevt_set_periodic(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) clkevt_periodic = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) nmdk_clkevt_reset();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static void nmdk_clksrc_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) writel(0, mtu_base + MTU_CR(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* ClockSource: configure load and background-load, and fire it up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) writel(nmdk_cycle, mtu_base + MTU_LR(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) writel(nmdk_cycle, mtu_base + MTU_BGLR(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) writel(clk_prescale | MTU_CRn_32BITS | MTU_CRn_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) mtu_base + MTU_CR(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static void nmdk_clkevt_resume(struct clock_event_device *cedev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) nmdk_clkevt_reset();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) nmdk_clksrc_reset();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static struct clock_event_device nmdk_clkevt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .name = "mtu_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .features = CLOCK_EVT_FEAT_ONESHOT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) CLOCK_EVT_FEAT_PERIODIC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) CLOCK_EVT_FEAT_DYNIRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .rating = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .set_state_shutdown = nmdk_clkevt_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .set_state_periodic = nmdk_clkevt_set_periodic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .set_state_oneshot = nmdk_clkevt_set_oneshot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .set_next_event = nmdk_clkevt_next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .resume = nmdk_clkevt_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * IRQ Handler for timer 1 of the MTU block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct clock_event_device *evdev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) evdev->event_handler(evdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int __init nmdk_timer_init(void __iomem *base, int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct clk *pclk, struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int min_ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) mtu_base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) BUG_ON(clk_prepare_enable(pclk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) BUG_ON(clk_prepare_enable(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * for ux500, and in one specific Ux500 case 32768 Hz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * Use a divide-by-16 counter if the tick rate is more than 32MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * At 32 MHz, the timer (with 32 bit counter) can be programmed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * with 16 gives too low timer resolution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (rate > 32000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) rate /= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) clk_prescale = MTU_CRn_PRESCALE_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) clk_prescale = MTU_CRn_PRESCALE_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Cycles for periodic mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) nmdk_cycle = DIV_ROUND_CLOSEST(rate, HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Timer 0 is the free running clocksource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) nmdk_clksrc_reset();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ret = clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) rate, 200, 32, clocksource_mmio_readl_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) pr_err("timer: failed to initialize clock source %s\n", "mtu_0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) sched_clock_register(nomadik_read_sched_clock, 32, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Timer 1 is used for events, register irq and clockevents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (request_irq(irq, nmdk_timer_interrupt, IRQF_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) "Nomadik Timer Tick", &nmdk_clkevt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) pr_err("%s: request_irq() failed\n", "Nomadik Timer Tick");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) nmdk_clkevt.cpumask = cpumask_of(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) nmdk_clkevt.irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (rate < 100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) min_ticks = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) min_ticks = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) clockevents_config_and_register(&nmdk_clkevt, rate, min_ticks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 0xffffffffU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) mtu_delay_timer.read_current_timer = &nmdk_timer_read_current_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) mtu_delay_timer.freq = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) register_current_timer_delay(&mtu_delay_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int __init nmdk_timer_of_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) pr_err("Can't remap registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) pclk = of_clk_get_by_name(node, "apb_pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (IS_ERR(pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) pr_err("could not get apb_pclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return PTR_ERR(pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) clk = of_clk_get_by_name(node, "timclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) pr_err("could not get timclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) irq = irq_of_parse_and_map(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) pr_err("Can't parse IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return nmdk_timer_init(base, irq, pclk, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) TIMER_OF_DECLARE(nomadik_mtu, "st,nomadik-mtu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) nmdk_timer_of_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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