Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) //  Copyright (C) 2000-2001 Deep Blue Solutions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) //  Copyright (C) 2002 Shane Nay (shane@minirl.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) //  Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) //  Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) //  Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/stmp_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * There are 2 versions of the timrot on Freescale MXS-based SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * The v1 on MX23 only gets 16 bits counter, while v2 on MX28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * extends the counter to 32 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * The implementation uses two timers, one for clock_event and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * another for clocksource. MX28 uses timrot 0 and 1, while MX23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * uses 0 and 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define MX23_TIMROT_VERSION_OFFSET	0x0a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define MX28_TIMROT_VERSION_OFFSET	0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define BP_TIMROT_MAJOR_VERSION		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define BV_TIMROT_VERSION_1		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define BV_TIMROT_VERSION_2		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define timrot_is_v1()	(timrot_major_version == BV_TIMROT_VERSION_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * There are 4 registers for each timrotv2 instance, and 2 registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * for each timrotv1. So address step 0x40 in macros below strides
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * one instance of timrotv2 while two instances of timrotv1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  * As the result, HW_TIMROT_XXXn(1) defines the address of timrot1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * on MX28 while timrot2 on MX23.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /* common between v1 and v2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define HW_TIMROT_ROTCTRL		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define HW_TIMROT_TIMCTRLn(n)		(0x20 + (n) * 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) /* v1 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define HW_TIMROT_TIMCOUNTn(n)		(0x30 + (n) * 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) /* v2 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define HW_TIMROT_RUNNING_COUNTn(n)	(0x30 + (n) * 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define HW_TIMROT_FIXED_COUNTn(n)	(0x40 + (n) * 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define BM_TIMROT_TIMCTRLn_RELOAD	(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define BM_TIMROT_TIMCTRLn_UPDATE	(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define BM_TIMROT_TIMCTRLn_IRQ_EN	(1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define BM_TIMROT_TIMCTRLn_IRQ		(1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define BP_TIMROT_TIMCTRLn_SELECT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL		0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL		0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS	0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static struct clock_event_device mxs_clockevent_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) static void __iomem *mxs_timrot_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) static u32 timrot_major_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static inline void timrot_irq_disable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	__raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN, mxs_timrot_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		     HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static inline void timrot_irq_enable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	__raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN, mxs_timrot_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		     HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static void timrot_irq_acknowledge(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	__raw_writel(BM_TIMROT_TIMCTRLn_IRQ, mxs_timrot_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		     HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) static u64 timrotv1_get_cycles(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	return ~((__raw_readl(mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 			& 0xffff0000) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static int timrotv1_set_next_event(unsigned long evt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 					struct clock_event_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	/* timrot decrements the count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	__raw_writel(evt, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int timrotv2_set_next_event(unsigned long evt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 					struct clock_event_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	/* timrot decrements the count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	__raw_writel(evt, mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static irqreturn_t mxs_timer_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct clock_event_device *evt = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	timrot_irq_acknowledge();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	evt->event_handler(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void mxs_irq_clear(char *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	/* Disable interrupt in timer module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	timrot_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	/* Set event time into the furthest future */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	if (timrot_is_v1())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		__raw_writel(0xffff, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		__raw_writel(0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			     mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	/* Clear pending interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	timrot_irq_acknowledge();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	pr_debug("%s: changing mode to %s\n", __func__, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int mxs_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	mxs_irq_clear("shutdown");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int mxs_set_oneshot(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	if (clockevent_state_oneshot(evt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		mxs_irq_clear("oneshot");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	timrot_irq_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static struct clock_event_device mxs_clockevent_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	.name			= "mxs_timrot",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	.features		= CLOCK_EVT_FEAT_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	.set_state_shutdown	= mxs_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	.set_state_oneshot	= mxs_set_oneshot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	.tick_resume		= mxs_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	.set_next_event		= timrotv2_set_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	.rating			= 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int __init mxs_clockevent_init(struct clk *timer_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (timrot_is_v1())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		mxs_clockevent_device.set_next_event = timrotv1_set_next_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	mxs_clockevent_device.cpumask = cpumask_of(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	clockevents_config_and_register(&mxs_clockevent_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 					clk_get_rate(timer_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 					timrot_is_v1() ? 0xf : 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 					timrot_is_v1() ? 0xfffe : 0xfffffffe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static struct clocksource clocksource_mxs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	.name		= "mxs_timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	.rating		= 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	.read		= timrotv1_get_cycles,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	.mask		= CLOCKSOURCE_MASK(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static u64 notrace mxs_read_sched_clock_v2(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	return ~readl_relaxed(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static int __init mxs_clocksource_init(struct clk *timer_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	unsigned int c = clk_get_rate(timer_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	if (timrot_is_v1())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		clocksource_register_hz(&clocksource_mxs, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		clocksource_mmio_init(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 			"mxs_timer", c, 200, 32, clocksource_mmio_readl_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		sched_clock_register(mxs_read_sched_clock_v2, 32, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int __init mxs_timer_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	struct clk *timer_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	mxs_timrot_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	WARN_ON(!mxs_timrot_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	timer_clk = of_clk_get(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	if (IS_ERR(timer_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		pr_err("%s: failed to get clk\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		return PTR_ERR(timer_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	ret = clk_prepare_enable(timer_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	 * Initialize timers to a known state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	stmp_reset_block(mxs_timrot_base + HW_TIMROT_ROTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	/* get timrot version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	timrot_major_version = __raw_readl(mxs_timrot_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			(of_device_is_compatible(np, "fsl,imx23-timrot") ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 						MX23_TIMROT_VERSION_OFFSET :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 						MX28_TIMROT_VERSION_OFFSET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	timrot_major_version >>= BP_TIMROT_MAJOR_VERSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	/* one for clock_event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	__raw_writel((timrot_is_v1() ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			BM_TIMROT_TIMCTRLn_UPDATE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			BM_TIMROT_TIMCTRLn_IRQ_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	/* another for clocksource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	__raw_writel((timrot_is_v1() ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 			BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			BM_TIMROT_TIMCTRLn_RELOAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 			mxs_timrot_base + HW_TIMROT_TIMCTRLn(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	/* set clocksource timer fixed count to the maximum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	if (timrot_is_v1())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		__raw_writel(0xffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 			mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		__raw_writel(0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 			mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	/* init and register the timer to the framework */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	ret = mxs_clocksource_init(timer_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	ret = mxs_clockevent_init(timer_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	/* Make irqs happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	irq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	if (irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	return request_irq(irq, mxs_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 			   "MXS Timer Tick", &mxs_clockevent_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) TIMER_OF_DECLARE(mxs, "fsl,timrot", mxs_timer_init);