^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2015 ARM Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Vladimir Murzin <vladimir.murzin@arm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TIMER_CTRL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TIMER_CTRL_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TIMER_CTRL_IE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TIMER_VALUE 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TIMER_RELOAD 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TIMER_INT 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct clockevent_mps2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 clock_count_per_tick;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct clock_event_device clkevt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static void __iomem *sched_clock_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static u64 notrace mps2_sched_read(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) return ~readl_relaxed(sched_clock_base + TIMER_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static inline struct clockevent_mps2 *to_mps2_clkevt(struct clock_event_device *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return container_of(c, struct clockevent_mps2, clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static void clockevent_mps2_writel(u32 val, struct clock_event_device *c, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) writel_relaxed(val, to_mps2_clkevt(c)->reg + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static int mps2_timer_shutdown(struct clock_event_device *ce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) clockevent_mps2_writel(0, ce, TIMER_RELOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) clockevent_mps2_writel(0, ce, TIMER_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static int mps2_timer_set_next_event(unsigned long next, struct clock_event_device *ce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) clockevent_mps2_writel(next, ce, TIMER_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) clockevent_mps2_writel(TIMER_CTRL_IE | TIMER_CTRL_ENABLE, ce, TIMER_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static int mps2_timer_set_periodic(struct clock_event_device *ce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 clock_count_per_tick = to_mps2_clkevt(ce)->clock_count_per_tick;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) clockevent_mps2_writel(clock_count_per_tick, ce, TIMER_RELOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) clockevent_mps2_writel(clock_count_per_tick, ce, TIMER_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) clockevent_mps2_writel(TIMER_CTRL_IE | TIMER_CTRL_ENABLE, ce, TIMER_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static irqreturn_t mps2_timer_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct clockevent_mps2 *ce = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 status = readl_relaxed(ce->reg + TIMER_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (!status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) pr_warn("spurious interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) writel_relaxed(1, ce->reg + TIMER_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ce->clkevt.event_handler(&ce->clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static int __init mps2_clockevent_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct clk *clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct clockevent_mps2 *ce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) const char *name = "mps2-clkevt";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ret = of_property_read_u32(np, "clock-frequency", &rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) clk = of_clk_get(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ret = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) pr_err("failed to get clock for clockevent: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) pr_err("failed to enable clock for clockevent: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) goto out_clk_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ret = -EADDRNOTAVAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) pr_err("failed to map register for clockevent: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) goto out_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) irq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (!irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ret = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) pr_err("failed to get irq for clockevent: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) goto out_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ce = kzalloc(sizeof(*ce), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (!ce) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) goto out_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ce->reg = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ce->clock_count_per_tick = DIV_ROUND_CLOSEST(rate, HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ce->clkevt.irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ce->clkevt.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ce->clkevt.rating = 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ce->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ce->clkevt.cpumask = cpu_possible_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ce->clkevt.set_state_shutdown = mps2_timer_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ce->clkevt.set_state_periodic = mps2_timer_set_periodic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ce->clkevt.set_state_oneshot = mps2_timer_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ce->clkevt.set_next_event = mps2_timer_set_next_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Ensure timer is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) writel_relaxed(0, base + TIMER_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ret = request_irq(irq, mps2_timer_interrupt, IRQF_TIMER, name, ce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) pr_err("failed to request irq for clockevent: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) goto out_kfree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) clockevents_config_and_register(&ce->clkevt, rate, 0xf, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) out_kfree:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) kfree(ce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) out_iounmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) out_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* clk_{disable, unprepare, put}() can handle NULL as a parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) out_clk_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static int __init mps2_clocksource_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct clk *clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) const char *name = "mps2-clksrc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ret = of_property_read_u32(np, "clock-frequency", &rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) clk = of_clk_get(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ret = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) pr_err("failed to get clock for clocksource: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) pr_err("failed to enable clock for clocksource: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) goto out_clk_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ret = -EADDRNOTAVAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) pr_err("failed to map register for clocksource: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) goto out_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Ensure timer is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) writel_relaxed(0, base + TIMER_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* ... and set it up as free-running clocksource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) writel_relaxed(0xffffffff, base + TIMER_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) writel_relaxed(0xffffffff, base + TIMER_RELOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) writel_relaxed(TIMER_CTRL_ENABLE, base + TIMER_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ret = clocksource_mmio_init(base + TIMER_VALUE, name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) rate, 200, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) clocksource_mmio_readl_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) pr_err("failed to init clocksource: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) goto out_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) sched_clock_base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) sched_clock_register(mps2_sched_read, 32, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) out_iounmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) out_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* clk_{disable, unprepare, put}() can handle NULL as a parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) out_clk_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int __init mps2_timer_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static int has_clocksource, has_clockevent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (!has_clocksource) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ret = mps2_clocksource_init(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) has_clocksource = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (!has_clockevent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ret = mps2_clockevent_init(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) has_clockevent = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) TIMER_OF_DECLARE(mps2_timer, "arm,mps2-timer", mps2_timer_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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