^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define pr_fmt(fmt) "mips-gic-timer: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/notifier.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/percpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/mips-cps.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static int gic_timer_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static unsigned int gic_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static bool __read_mostly gic_clock_unstable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static void gic_clocksource_unstable(char *reason);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static u64 notrace gic_read_count_2x32(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned int hi, hi2, lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) hi = read_gic_counter_32h();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) lo = read_gic_counter_32l();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) hi2 = read_gic_counter_32h();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) } while (hi2 != hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) return (((u64) hi) << 32) + lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static u64 notrace gic_read_count_64(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return read_gic_counter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static u64 notrace gic_read_count(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (mips_cm_is64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return gic_read_count_64();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return gic_read_count_2x32();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static int gic_next_event(unsigned long delta, struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int cpu = cpumask_first(evt->cpumask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u64 cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) cnt = gic_read_count();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) cnt += (u64)delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (cpu == raw_smp_processor_id()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) write_gic_vl_compare(cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) write_gic_vl_other(mips_cm_vp_id(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) write_gic_vo_compare(cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) res = ((int)(gic_read_count() - cnt) >= 0) ? -ETIME : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static irqreturn_t gic_compare_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct clock_event_device *cd = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) write_gic_vl_compare(read_gic_vl_compare());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) cd->event_handler(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static struct irqaction gic_compare_irqaction = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .handler = gic_compare_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .percpu_dev_id = &gic_clockevent_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .flags = IRQF_PERCPU | IRQF_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .name = "timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static void gic_clockevent_cpu_init(unsigned int cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct clock_event_device *cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) cd->name = "MIPS GIC";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) cd->features = CLOCK_EVT_FEAT_ONESHOT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) CLOCK_EVT_FEAT_C3STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) cd->rating = 350;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) cd->irq = gic_timer_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) cd->cpumask = cpumask_of(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) cd->set_next_event = gic_next_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) clockevents_config_and_register(cd, gic_frequency, 0x300, 0x7fffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) enable_percpu_irq(gic_timer_irq, IRQ_TYPE_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void gic_clockevent_cpu_exit(struct clock_event_device *cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) disable_percpu_irq(gic_timer_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static void gic_update_frequency(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned long rate = (unsigned long)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) clockevents_update_freq(this_cpu_ptr(&gic_clockevent_device), rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int gic_starting_cpu(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) gic_clockevent_cpu_init(cpu, this_cpu_ptr(&gic_clockevent_device));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int gic_clk_notifier(struct notifier_block *nb, unsigned long action,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct clk_notifier_data *cnd = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (action == POST_RATE_CHANGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) gic_clocksource_unstable("ref clock rate change");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) on_each_cpu(gic_update_frequency, (void *)cnd->new_rate, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int gic_dying_cpu(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) gic_clockevent_cpu_exit(this_cpu_ptr(&gic_clockevent_device));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static struct notifier_block gic_clk_nb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .notifier_call = gic_clk_notifier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static int gic_clockevent_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (!gic_frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ret = setup_percpu_irq(gic_timer_irq, &gic_compare_irqaction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) pr_err("IRQ %d setup failed (%d)\n", gic_timer_irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) cpuhp_setup_state(CPUHP_AP_MIPS_GIC_TIMER_STARTING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) "clockevents/mips/gic/timer:starting",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) gic_starting_cpu, gic_dying_cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static u64 gic_hpt_read(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return gic_read_count();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static struct clocksource gic_clocksource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .name = "GIC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .read = gic_hpt_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .flags = CLOCK_SOURCE_IS_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .vdso_clock_mode = VDSO_CLOCKMODE_GIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static void gic_clocksource_unstable(char *reason)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (gic_clock_unstable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) gic_clock_unstable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) pr_info("GIC timer is unstable due to %s\n", reason);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) clocksource_mark_unstable(&gic_clocksource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int __init __gic_clocksource_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned int count_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Set clocksource mask. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) count_width = read_gic_config() & GIC_CONFIG_COUNTBITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) count_width >>= __ffs(GIC_CONFIG_COUNTBITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) count_width *= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) count_width += 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) gic_clocksource.mask = CLOCKSOURCE_MASK(count_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* Calculate a somewhat reasonable rating value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) gic_clocksource.rating = 200 + gic_frequency / 10000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ret = clocksource_register_hz(&gic_clocksource, gic_frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) pr_warn("Unable to register clocksource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int __init gic_clocksource_of_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (!mips_gic_present() || !node->parent ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) !of_device_is_compatible(node->parent, "mti,gic")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) pr_warn("No DT definition\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) clk = of_clk_get(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (!IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) pr_err("Failed to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) gic_frequency = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) } else if (of_property_read_u32(node, "clock-frequency",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) &gic_frequency)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) pr_err("Frequency not specified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) gic_timer_irq = irq_of_parse_and_map(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (!gic_timer_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) pr_err("IRQ not specified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ret = __gic_clocksource_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ret = gic_clockevent_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (!ret && !IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (clk_notifier_register(clk, &gic_clk_nb) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) pr_warn("Unable to register clock notifier\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* And finally start the counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) clear_gic_config(GIC_CONFIG_COUNTSTOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * It's safe to use the MIPS GIC timer as a sched clock source only if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * its ticks are stable, which is true on either the platforms with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * stable CPU frequency or on the platforms with CM3 and CPU frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * change performed by the CPC core clocks divider.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (mips_cm_revision() >= CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) sched_clock_register(mips_cm_is64 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) gic_read_count_64 : gic_read_count_2x32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 64, gic_frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) TIMER_OF_DECLARE(mips_gic_timer, "mti,gic-timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) gic_clocksource_of_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags